PCI Express® Technology: The Ubiquitous I/O Interconnect, Now in its Fifth Generation

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Thursday, September 14, 2017
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The Peripheral Component Interconnect (PCI) architecture has been the cornerstone for I/O connectivity spanning two decades. What started off as the I/O interconnect for personal computers has evolved to be the ubiquitous I/O interconnect for server, client, embedded, IoT, and mobile market segments. The PCI Express® (PCIe®) architecture, currently in its fifth generation is the attach point for storage, networking and a wide range of external I/O controllers.

This paper delves into the latest PCIe architecture innovations in hardware, software, and electromechanical form factors. The fifth generation signaling technology at 32GT/s doubles per-pin bandwidth in a power-efficient manner while maintaining full backwards compatibility with the prior four generations. Architected re-timers form an essential ingredient for long reach channels and non-destructive, run-time receiver margining helps with predictive fault analysis and repair.

The PCIe specification continues to provide architectural improvements to reduce system latencies, lower power (active and idle), enhance I/O virtualization needs, and support low cost flexible platform integration. The PCI-SIG® robust compliance program ensures plug-and-play interoperability across a wide range of platforms using common components. These innovations will enable the continued evolution of PCIe technology.

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