Solving NVMe/PCIe Issues with NVMe-oF with a Smart I/O Processor

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Publish Date: 
Wednesday, September 13, 2017
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The introduction of the NVMe protocol promises performances that are up to 7x times better than SAS SSDs. But its introduction raises new challenges:
First, the introduction of NVMe implies the use of PCIe for connecting JBOFs to storage server nodes. PCIe was initially designed to be an efficient CPU-to-peripheral bus. It was not, however, intended to scale outside the chassis and into the datacenter. PCIe requires custom PCIe adapters and cables, limited scalability and touchy hot plug support.

Second, as performance increases by an order of magnitude, the bottlenecks shift from the disks themselves to the CPU, DDR and network.

Our presentation will touch on the challenges facing storage racks with integrated SSDs. We will present a possible solution for these challenges that would allow storage architects to optimize their system by using a combination of the NVMe-oF protocol with a smart I/O processor. This would solve the interconnect issues while combining the performance of the NVMe protocol and the ease of Ethernet connectivity.

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