SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Anjaneya ‘Reddy’ Chagam
Principal Engineer and Chief SDS Architect, Intel’s Data Center Group / Board Member at SODA Foundation
Intel Corp.
Anjaneya “Reddy” Chagam is a Senior Principal Engineer and Lead Cloud Storage Architect in Intel’s Cloud and Enterprise Solutions Group. He is responsible for developing software-defined storage strategy, architecture, and technology initiatives. He was a member of the Technical Steering Committee for the OpenSDS Project and he represents Intel on the Ceph board. He is a Chief Architect responsible for delivering software optimizations in Ceph via Intel upstream contributions. He is a regular speaker at major industry conferences, including Storage Developer Conference, OpenStack, CloudNativeCon and Red Hat Summit, has published several white papers on flash-optimized storage solutions. He earned an MS in computer science from Arizona State University.
Related Sessions
Rethinking Software Defined Memory (SDM) for large-scale applications with faster interconnects and memory technologies
Software-Defined Memory (SDM) is an emerging architecture paradigm that provides software abstraction between applications and underlying memory resources with dynamic memory provisioning to achieve the desired SLA. With emergence of newer memory technologies and faster interconnects, it is possible to optimize memory resources deployed in cloud infrastructure while achieving best possible TCO. SDM provides a mechanism to pool disjoint memory domains into a unified memory namespace. SDM foundation architecture and implementation framework is currently being developed in OCP Future Technology Initiative (FTI-SDM) project. Goal for this talk is to share OCP work and explore deeper collaboration with SNIA. This talk will cover SDM Architecture, current industry landscape, academic research and leading use cases (e.g. Memcached, databases etc.) that can benefit from SDM design. This talk will cover how applications can consume different tiers of memory (e.g., DDR, SCM, HBM) and interconnect technologies (e.g. CXL) that are foundational to SDM framework to provide load-store access for large scale application deployments. SDM value prop will be demonstrated with caching benchmarks and tiering to show how memory can be accessed transparently.
