SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Envisioning a Computational Storage Architecture with an SDXI Data Mover: Early Efforts
Abstract
SDXI is a standard for a memory-to-memory data mover and acceleration interface that is extensible, forward-compatible, and independent of I/O interconnect technology. Among other features, SDXI standardizes an interface and architecture that can be abstracted or virtualized with a well-defined capability to quiesce, suspend, and resume the architectural state of a per-address-space data mover.
Computational Storage is a SNIA standard that defines architectures for offloading the host or reducing data movement. Compute resources residing on a storage device or very near a storage device perform computations on data instead of the host. Computational Storage reduces bandwidth and power requirements of the storage fabric and frees the host for other purposes.
While reducing data movement and offloading the host remains the goal, there are times when data needs to move to the compute or results need to move to the host. The SNIA SDXI+CS Subgroup is a new working group exploring the architectural possibilities of combining SDXI with Computational Storage. This presentation will share our current thinking and architectural explorations around unifying Computational Storage and SDXI as well as the use cases for SDXI-based Computational Storage devices.
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An important enabler of this design is the ability for pNFS clients to identify which pNFS data server holds a given file, allowing queries to be routed correctly. Complementing this is a recent Linux kernel enhancement that transparently localizes remote pNFS reads when a file is detected to be local. Together, these capabilities enable efficient query offload without exposing application code to internal filesystem structures—preserving abstraction boundaries and enforcing standard POSIX permissions. We demonstrate this architecture in a real-world scientific visualization pipeline, modified to leverage pushdown to query large-scale simulation data stored in Parquet, a popular columnar format the lab is adopting for its future workloads. We conclude with key performance results and future opportunities.
Host Addressing of NVMe Subsystem Local Memory
While a host has been able to address NVMe device memory using Controller Memory Buffer (CMB) and Persistent Memory Region (PMR), that memory has never been addressable by NVMe commands. NVMe introduced the Subsystem Local Memory IO Command Set (SLM), which allowed NVMe device memory to be addressable by NVMe commands; however, this memory could not be addressed by the host using host memory addresses. A new technical proposal is being developed by NVM Express that would allow SLM to be assigned to a host memory address range. We will describe the architecture of this new NVMe feature and discuss the benefits and use cases that host addressable SLM enables.
Integrating Computational Storage Devices into Storage Software Stacks
Storage systems leverage data transformations such as compression, checksums, and erasure coding. These transformations are necessary to save on capacity and protect against data loss. These transformations however are both memory bandwidth and CPU intensive. This is leading to a large disparity between the performance from the storage software layers and the storage devices backing the data. This disparity only continues to grow as NVMe devices provide increasing bandwidth with each new PCIe generation. Computational storage devices (accelerators) provide a path forward by offloading these resource intensive transformations to hardware designed to accelerate operations.
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