SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Smart Data Accelerator Interface (SDXI) is a proposed standard for a memory to memory data movement and acceleration interface. Software memcpy is the current data movement standard for software implementation due to stable CPU ISA. However, this takes away from application performance and incurs software overhead to provide context isolation. Offload DMA engines and their interface are vendor-specific and not standardized for user-level software. SNIA’s SDXI TWG is tasked with developing and standardizing an extensible, forward-compatible memory to memory data mover and acceleration interface that is independent of actual data mover implementations and underlying I/O interconnect technology. In this panel discussion, experts and representatives of SDXI TWG member companies will talk about their motivations in joining this industry-standard effort.
Smart Data Accelerator Interface (SDXI) is a proposed standard for a memory to memory data movement and acceleration interface. Software memcpy is the current data movement standard for software implementation due to stable CPU ISA. However, this takes away from application performance and incurs software overhead to provide context isolation. Offload DMA engines and their interface are vendor-specific and not standardized for user-level software. SNIA’s SDXI TWG is tasked with developing and standardizing an extensible, forward-compatible memory to memory data mover and acceleration interface that is independent of actual data mover implementations and underlying I/O interconnect technology. In this panel discussion, experts and representatives of SDXI TWG member companies will talk about their motivations in joining this industry-standard effort.
The first phase of the IBTA Memory Placement Extensions (MPE), supporting low-latency RDMA access to persistent memory on Infiniband and RoCE networks, was published in August. In this talk, the MPE will be introduced, motivations for the additions discussed, and performance advantages of the MPE over current techniques will be reviewed. In addition to the these new MPE protocol enhancements in the new specification, additional operations, currently under development and planned for the next version, will also be presented.
Software-Defined Memory (SDM) is an emerging architecture paradigm that provides software abstraction between applications and underlying memory resources with dynamic memory provisioning to achieve the desired SLA. With emergence of newer memory technologies and faster interconnects, it is possible to optimize memory resources deployed in cloud infrastructure while achieving best possible TCO. SDM provides a mechanism to pool disjoint memory domains into a unified memory namespace. SDM foundation architecture and implementation framework is currently being developed in OCP Future Technology Initiative (FTI-SDM) project. Goal for this talk is to share OCP work and explore deeper collaboration with SNIA. This talk will cover SDM Architecture, current industry landscape, academic research and leading use cases (e.g. Memcached, databases etc.) that can benefit from SDM design. This talk will cover how applications can consume different tiers of memory (e.g., DDR, SCM, HBM) and interconnect technologies (e.g. CXL) that are foundational to SDM framework to provide load-store access for large scale application deployments. SDM value prop will be demonstrated with caching benchmarks and tiering to show how memory can be accessed transparently.
Data center architectures continue to evolve rapidly to support the ever-growing demands of emerging workloads such as artificial intelligence, machine learning and deep learning. Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. CXL technology is designed to address the growing needs of high-performance computational workloads by supporting heterogeneous processing and memory systems for applications in artificial intelligence, machine learning, communication systems, and high-performance computing (HPC). These applications deploy a diverse mix of scalar, vector, matrix, and spatial architectures through CPU, GPU, FPGA, smart NICs, and other accelerators. During this session, attendees will learn about the next generation of CXL technology. The CXL 2.0 specification, announced in 2020, adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory. This presentation will explore the memory pooling features of CXL 2.0 and how CXL technology will meet the performance and latency demands of emerging workloads for data-hungry applications like AI and ML.
Adopting new memory technologies such as Persistent Memory and CXL-attached Memory is a challenge for software. While libraries and frameworks (such as PMDK) can help developers build new software around emerging technology, legacy software faces a more severe challenge. At IBM Research Almaden we are exploring a new approach to managing heterogeneous memory in the context of Python. Our solution, PyMM, focuses on ease-of-use and is aimed primarily at the data science community. This talk will outline PyMM and discuss how it is being used to manage Intel Optane persistent memory. We will review the PyMM programming abstractions and some early data science use-cases. PyMM is currently an early research prototype with open source availability.
Over the past nearly three decades, PCI-SIG® has delivered a succession of industry-leading specifications that remain ahead of the curve of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in diverse market segments, including data centers, PCs and automotive applications. Each new PCI Express® (PCIe®) specification consistently delivers enhanced performance, unprecedented speeds, and low latency – doubling the data rate over previous generations. The PCIe 6.0 specification – targeted for final release in 2021 – will deliver 64 GT/s data rate (256 GB/s via x16 configuration), while maintaining backward compatibility with previous generations. In this session, attendees will learn the nuts and bolts of PCIe 6.0 architecture and how it will enable high-performance networking. Some key features of the upcoming specification include PAM4 encoding, low-latency Forward Error Correction (FEC), and backward compatibility with all previous generations of PCIe technology. This presentation will also highlight PCIe 6.0 technology use cases and the heterogenous computing applications that will be accelerated by PCIe 6.0 technology, including artificial intelligence, machine learning and deep learning. Finally, attendees will receive an update on the release timeline of the PCIe 6.0 specification later this year and rollout of the interoperability and compliance program.