SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Dr. Debendra Das Sharma
Intel Fellow
Intel Corporation
Dr. Debendra Das Sharma is an Intel Fellow in the Data Platforms Group and director of the I/O Technology and Standards Group at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. Dr. Das Sharma’s team delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Intel’s Coherency interconnect, and multichip package interconnect. He is a key driver of external standards for PCIe and CXL, and internal proprietary interfaces, as well as implementation.
Dr. Das Sharma joined Intel in 2001 as a technical lead in the Advanced Components Division, designing server chipsets. He previously worked with Hewlett-Packard, where he led development of their server chipsets. He holds 137 US patents and is a frequent keynote speaker, distinguished lecturer, invited speaker, and panelist at the PCI-SIG Developers Conference, CXL consortium events, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, SNIA SDC, and Intel Developer Forum.
Dr. Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force. Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur.
Related Sessions
Innovations in Load-Store I/O Causing Profound Changes in Memory, Storage, and Compute Landscape
Emerging and existing applications with cloud computing, 5G, IoT, automotive, and high-performance computing are causing an explosion of data. This data needs to be processed, moved, and stored in a secure, reliable, available, cost-effective, and power-efficient manner. Heterogeneous processing, tiered memory and storage architecture, accelerators, and infrastructure processing units are essential to meet the demands of this evolving compute, memory, and storage landscape. These requirements are driving significant innovations across compute, memory, storage, and interconnect technologies. Compute Express Link* (CXL) with its memory and coherency semantics on top of PCI Express* (PCIe) is paving the way for the convergence of memory and storage with near memory compute capability. Pooling of resources with CXL will lead to rack-scale efficiency with efficient low-latency access mechanisms across multiple nodes in a rack with advanced atomics, acceleration, smart NICs, and persistent memory support. In this talk we will explore how the evolution in load-store interconnects will profoundly change the memory, storage, and compute landscape going forward.