Speaker 2026 directory

Nate is Soldigm’s Sr. Director of AI Solutions and Software. Nate brings 30 years of experience across storage, cloud, and software. Nate is a co-founder of the Storage Performance Development Kit (SPDK) and the Intelligent Storage Acceleration Library (ISA L). Nate also has led key open source contributions to projects such as Ceph, OpenStack Swift, RocksDB and later drove research, development and operations of cloud storage infrastructure for Intel’s Tiber AI Cloud services business.

S. Windh received a Ph.D. in computer science from the University of California (Riverside, California, USA) in 2018. He was a Research Assistant at the Embedded Systems Lab during his studies.
He is currently an MTS Systems Software Engineering in the TPG Storage and Memory Systems Pathfinding group at Micron Technology, Inc. (Richardson, Texas USA). His research interests include multithreading and parallelism, reconfigurable-computing architectures and tools, and high-performance computing and applications. 
He co-led the Software Architecture for Micron's Memory Lake investigation with Pacific Northwest National Labs exploring disaggregated shared memory with near memory compute capabilities. He is currently leading a project exploring emulating High IOPS storage drives for AI workloads and extending Nvidia’s Dynamo to support CXL shared memory.

Jacob Schmier is a Senior Technologist in Firmware Engineering at Sandisk, developing enterprise SSD firmware for next‑generation platforms. His work centers on implementation and technical leadership driving performance, reliability, and efficiency in data‑center storage.

Gaurav Agarwal is a Senior Distinguished Engineer at Marvell, where he leads the Memory and Storage Solutions team focused on next-generation AI infrastructure and open software standards. Over a 30-year career—including a decade at Marvell—he has delivered transformative contributions across storage, networking, and accelerated computing. 

Gaurav Agarwal is a Senior Distinguished Engineer at Marvell, where he leads the Memory and Storage Solutions team focused on next-generation AI infrastructure and open software standards. Over a 30-year career—including a decade at Marvell—he has delivered transformative contributions across storage, networking, and accelerated computing. 

Brian Atkinson is a HPC Engineer at Los Alamos National Lab in the HPC-DES. His research is focused on next generation storage systems at LANL. Brian has worked on building fast storage endpoints, which leverage new and emerging storage technologies. He has made contributions to various open-source file system projects. He led the source code development of adding Direct I/O support to ZFS. His work has focused on improving performance and efficiencies with distributed file systems.

Curtis Ballard is a Distinguished Technologist with Hewlett Packard Enterprise in the HPE Storage organization where he works on storage architecture, intellectual property, and storage technology strategy with a focus on enabling new storage technologies. Curtis has 30 years of experience in storage and storage interfaces technologies where he has worked in product design teams for storage arrays, storage enclosures, tape drives, tape libraries, and magneto optical drives. He has developed hardware designs for storage interfaces and storage controllers as well as firmware for motion control, storage interfaces, user interface, and embedded operating systems. In addition to Storage Platform development for HPE, Curtis also represents HPE in several industry organizations. Curtis is a treasurer for the NVM Express Board of Directors, is a member of the SNIA Technical Council, and is the vice-chair of the INCITS/SCSI (T10) Storage Interfaces Technical Committee where he has been the editor for several SCSI standards. He is an inventor on over 40 US patents in the storage industry across electrical, software, and mechanical disciplines.

Stephen Bates is an Fellow in the AI Business Unit at AMD, where he leads work on communication and storage architectures and associated software for AI and data-centric systems. He is a recognized expert in high-performance technologies including NVMe, RDMA, TCP/IP, and non-volatile memory, with deep experience developing complex storage and communication solutions such as NVMe controllers and PCIe switching fabrics.

Stephen thrives at the intersection of hardware and software, bridging architectural innovation with practical implementation. He is an active contributor to the Linux kernel and other open-source projects that advance system performance and scalability.

Prior to AMD, Stephen served as Assistant Professor of Computer Engineering at the University of Alberta. He holds a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Filip Blagojevic is a Research Scientist at Western Digital. His research focuses on storage systems, high-performance computing, distributed systems, and system-level optimization for data-intensive workloads. He received his PhD in Computer Science from Virginia Tech in 2008 and previously worked at Lawrence Berkeley National Laboratory.

His recent work explores storage and systems support for emerging AI workloads, including LLM inference, KV-cache management, and memory/storage tiering. He has also worked extensively on Linux file systems, HDD-SMR storage, Hadoop/HDFS, erasure coding, and performance characterization of large-scale storage systems.

Thomas Boone, Ph.D. is a Distinguished Engineer at Western Digital where he manages defense and aerospace research program. He leads the company’s performance of the United States Air Force Research Lab ANGSTRM program to develop the next-generation strategically rad-hard memory for the DoD. With over 20 years experience in R&D management and technical leadership within the microelectronics and data storage industries, he specifically focuses on HiRel rad-hard microelectronic solutions for defense and aerospace applications. Dr. Boone received his Ph.D. in AP/EE from Yale University in 2004, MSEE from Purdue University in 1998 and BSEE from U.T. Arlington in 1994. He has over 20 issued U.S. patents and co-author of 26 peer-reviewed journal articles.

Jeff Bromberger is an engineer on the Storage Core team at Microsoft. Prior to joining Microsoft in 2023, he was co-owner of Kernel Drivers and worked as a Windows driver consultant for over 20 years.

Satananda Burla is a Distinguished Engineer at Marvell, involved in the design and development of Marvell Octeon SoC architecture. He is also involved in the design and development of Networking, Memory/Storage, and Security solutions involving multiple Marvell product lines. He represents Marvell at OPI, OASIS, IBTA, UEC, and other technical forums.

Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Core Datacenter Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP, serves on the SNIA board, and co-chairs the SFF TWG and community.  Anthony has over 26 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Clarete Crasta is a Principal Engineer in Hewlett Packard Enterprise, currently working in the HPC and AI Advance Development group. She is a well-recognized technical architect and has built a solid reputation over 20 years with deep system software expertise in High Performance Computing, memory and storage technologies, operating systems kernel, platform & IO, and virtualization. Her ability to drive and lead teams, focus on customers, willingness to take up any complex work in newer areas, effective communication skills, and active collaboration has gained her acceptance across the community. Clarete has experience leading and collaborating across teams, business units,  customers and partners. She is a co-inventor on 13 US filed patents and has co-authored 7 publications. She has presented at various conferences such as SNIA CMS, SNIA SDC, CUG, GHCI on Fabric Attached Memory and related topics. She has worked as a member of the technical committee and review board for GHCI, IEEE and is serving as Industry Track Chair for IC2E. She holds a master’s degree in software engineering and bachelor’s in electrical engineering

Frank Ferro is the group director of product marketing at Cadence Design Systems responsible for memory interface IP products. Frank joined Cadence after spending 25+ years at Rambus, AT&T, Lucent, and Agere Systems. Mr. Ferro holds an executive MBA from the Fuqua School of Business at Duke University, an M.S. in computer science, and a B.S. in electronic engineering technology from the New Jersey Institute of Technology.

Steve French is a member of the Samba team, and Principal Software Engineer at Microsoft (Azure Storage), and long time maintainer (as well as original author) of one of the more active Linux file systems (cifs.ko), and a frequent presenter at SMB and storage conferences. He is also co-maintainer of the Linux kernel server (ksmbd). He was formerly chair of the SNIA CIFS Working group and co-author of the SNIA CIFS Specification. Formerly he was File System Architect for the IBM Linux Technology Center.

Katya Giannios is a Principal Machine Learning Engineer in the TPG Pathfinding & Strategy- Storage and Memory Systems Group at Micron Technology. Her work involves profiling and analysis of commercial workloads with emphasis on AI software-hardware co-designed applications. Katya holds a Ph.D. in Applied Mathematics, from the Technical University of Munich (TUM) in collaboration with the Max-Planck Institute for Plasma Physics, Munich, Germany. After completing her academic journey, Katya transitioned into the dynamic world of data science. She has gained extensive experience across various industries, from finance with Allianz Global Investment to university at Purdue University

Jason is a Distinguished Engineer at Dell Technologies, working in the Storage Chief Technology Office. His role involves leading the development of next-generation storage and network protocols for both Public and Private Clouds. Jason also serves as Chair of the SNIA Accelerated Object I/O Technical Working Group. Throughout his career, Jason has focused on enterprise storage and meeting the needs of customers who want to expand beyond the traditional on-premises data center. He enjoys collaborating with customers and partners to understand their requirements when transforming their business. In his personal life, Jason is passionate about running marathons and baking artisan bread. He lives in Newton, Massachusetts, with his wife and their three children.

Alessandro Goncalves is a Storage Solutions Architect specializing in high-performance storage systems, AI/ML infrastructure, and workload-aware performance engineering. Currently at Solidigm, he focuses on architecting and benchmarking SSD-based solutions for emerging AI and inference workloads, collaborating with organizations such as MLCommons to evaluate next-generation storage behavior for data-intensive AI pipelines.

His background includes persistent memory architecture and performance engineering work at Intel, where he contributed to solutions involving Optane and large-scale storage performance analysis across enterprise and hyperscale environments. His recent work centers on AI-oriented storage observability, workload fingerprinting, vector database benchmarking, KV-cache infrastructure, and cross-layer latency attribution for modern storage systems.

Jack Guedj is co-founder and CEO of Numem, Inc., a provider of low-power Memory/SOC Subsystem IP Cores (based on MRAM), Chiplets and Turnkey Custom Chips. Beginning in 2008, Jack was President and CEO of Tensilica, leading it to the #1 position in merchant DSPs and, the acquisition by Cadence in 2013. Jack was then Cadence Corporate VP, Tensilica Products. Prior to Tensilica Jack led the spin-out of Magnum from Cirrus Logic, serving as founder, president and CEO. Prior to Cirrus, he was president of Tvia, Inc., leading that company's successful IPO in August 2000. Jack holds an MBA from the UCLA Graduate School of Management, an MSEE from Pierre & Marie Curie Engineering School of Paris, and a doctoral degree from the University of Pierre & Marie Curie.

Kalyan Gunda is a Senior Distinguished Engineer and Chief Architect for Unstructured Storage at Dell Technologies, focused on scalable object storage and distributed data platforms. He brings deep expertise across S3/object storage, distributed file systems, and data protection, helping enterprises simplify data infrastructure for modern, data‑intensive workloads. Kalyan works at the intersection of storage and AI, shaping how application‑driven, API‑first storage models enable scalable data pipelines for next‑generation workloads

Abhishek Gupta is a Storage Architect at Cerebras Systems, where he designs next-generation storage infrastructure for large-scale AI training and inference workloads. He brings over 15 years of experience building distributed storage systems, file systems, and high-performance I/O stacks. Previously, he worked as Senior Staff at Huawei's Research Centre, with earlier principal and senior engineering roles at Dell EMC (Isilon OneFS, Data Domain), DDN, NetApp, and Veritas. His work spans GPU Direct Storage, File-over-Memory, CXL, computational storage, and distributed file systems.

Steffen has more than 25 years of industry experience in product, technology, business & corporate development as well as strategy roles. He served as Senior Vice President, Business Development, Data Storage at Twist Bioscience and held executive management positions at various semiconductor companies including Western Digital, Everspin, SandForce, and Seagate Technology. At Everspin, Steffen was part of the Marketing team that drove the introduction of the world’s first commercial Spin-Torque MRAM product offering. He has been deeply engaged in various industry trade associations and standards organizations including cofounding the DNA Data Storage Alliance in 2020 as well as the USB Flash Drive Alliance, serving as their president from 2003 to 2007. He holds an Economic Electrical Engineering degree (EEE) from the Technical University of Darmstadt, Germany.

Brian Hirano is currently Vice President of Business Development at XCENA and has previously worked for Oracle, a hardware-accelerated data analytics startup, and Micron. Brian is a member of the SNIA AI Data Workload TWG.

Chih-Tsung Huang is the Senior Director of Hardware Engineering in the Common Hardware Group. Chih-Tsung is responsible for delivering Sustainable AI infrastructure solutions for silicon, hardware systems and optics in Cisco’s switching, routing, optical, access and IoT portfolios. Chih-Tsung has over 100 US and Global patents covering a breadth of topics including but not limited to sustainability, silicon, FPGA, networking, compute, security and storage.

20 years of experience working on parallel file systems

Thomas Jew is a Fellow at NXP and leads development of Non-Volatile Memory solutions for Advanced Microcontroller and Microprocessor applications. He has worked on discrete non-volatile memory products and embedded memory designs including traditional flash and emerging memory technologies integrated in microcontrollers for IOT and Automotive applications for 35+ years. Prior to joining NXP by way of Freescale Semiconductor/Motorola, he worked for Texas Instruments, designing discrete flash memories. Thomas received his BS and MS degrees in Electrical Engineering from Texas A&M University in 1988 and 1991 respectively.

Trent Johnson is a Hardware Architect at IBM, with a focus on the IBM FlashCore Module (Solid State Drive). He joined IBM as part of the Cleversafe Acquisition where he was the System Hardware Architect of exabyte-scale Object Storage. Prior to Cleversafe, he developed system-level manufacturing and test solutions for AMD CPUs and GPUs where he was awarded the AMD Corporate Technical Achievement Award. 
He has 27 years of industry experience, holds 7 US patents and has published at the Future of Memory and Storage, SNIA Developer Conference, Burn-in and Test Socket Workshop as well as the Conference for Consumer Electronics. He earned BSEE and MSEE degrees from The University of Texas at Austin in Electrical Engineering with a focus on Manufacturing System Engineering.

Kapil Karkra is a Sr. Principal Engineer at Solidigm responsible for software and solutions pathfinding for next-generation storage solutions supporting AI infrastructure. His work focuses on evolving Cloud Storage Acceleration Layer (CSAL), a host-based FTL with RAID and Caching, bringing technologies such as Mixed Media (MM) and Flexible Data Placement (FDP) to market, and defining turnkey reference architectures that integrate hardware and software to accelerate adoption of high-density NAND SSDs (QLC, PLC, and HLC) for AI workloads. Over his 25+ year career, he has advanced storage systems ranging from RAID, caching, and FTLs to distributed storage stacks at IBM, Intel, and Solidigm. Recently, he helped build AI cloud storage services at Intel, integrating technologies such as VAST Data Platform and MinIO AIStor. He has 35+ patent filings and 20+ issued patents, has authored numerous industry publications, and has contributed to industry standards including NVMe (e.g., Multiple Atomicity) and PCIe (e.g., Native PCIe Enclosure Management, NPEM). Kapil holds a bachelor's degree in electrical engineering from the National Institute of Technology (NIT), India, and an MBA from Arizona State University.

Keith MacLean is a Member of Technical Staff and System Architect at Micron Technology, where he focuses on enterprise SSD architecture, power efficiency, and next-generation storage platform design.

Pankaj Mehra is Professor of Research in Computer Science and Engineering department at The Ohio State University. He founded Elephance Memory, a company that builds software to optimize disaggregated data center memory for data infrastructure and applications. Pankaj has held executive positions in the Memory industry since 2013 when he took over as SVP and WW CTO of Fusion-io, later serving as VP and Senior Fellow at both acquirers SanDisk and Western Digital. Pankaj Mehra led SmartSSD (as VP of Product Planning) and other workload-optimized flash storage products (as VP of Storage Pathfinding) at Samsung, for which he and his team of 10 received Samsung's prestigious R&D Award in 2019. SmartSSD went on to win the CES R&D Innovation Award in 2021. Previously at Hewlett-Packard, Pankaj was promoted to HP Distinguished Technologist in 2004 for his pioneering work on RDMA-attached persistent memory devices and filesystems. Later he founded HP Labs Russia and served as its Chief Scientist until 2010. He is also the founder of startups IntelliFabric, Whodini and AwarenaaS. Pankaj's international experience spans academia, industry and government. His publications include 3 books and over 100 papers and patents. Pankaj holds Ph.D. in Computer Science from The University of Illinois at Urbana-Champaign.

Chris J. Newburn, who goes by CJ, is a Distinguished Engineer who drives HPC strategy and the technical IO roadmap in NVIDIA GPU Cloud, focused on pushing the envelope for storage and networking programming models at scale, data center architecture and security, and scaled systems.

He is a community builder with a passion for building an ecosystem that extends the core capabilities of hardware and software platforms from HPC into AI, data science, and visualization. He co-leads the Storage-Next effort to optimize products for IOPs/TCO.

He tinkers with and leverages NVIDIA and vendor products in a lab packed with scaled compute, storage and networking gear to apply and extend new tech. He's delighted to have worked on volume products that his Mom used and that help researchers do their life's work in science that previously wasn't possible.

Masood Noori is a Solution Technologist at Seagate focused on architecting AI infrastructure across NeoCloud and Sovereign Cloud ecosystems. He develops reference architectures that integrate mass-capacity storage into GPU-driven AI pipelines, enabling scalable and cost-efficient data foundations. Masood collaborates with hyperscalers, hardware vendors, and cloud-native partners to accelerate adoption of hybrid HDD–SSD architectures aligned to real-world workload demands. He focuses on turning storage into an active component of AI performance, economics, and lifecycle management as data growth and AI workloads scale globally.

Rohan Puri is a Senior Staff Engineer at DataDirect Networks (DDN), working on the Infinia IO Path. Previously he was a Staff Engineer at Samsung Semiconductor working on distributed file systems. He has worked across the Linux storage stack for over 14 years, including filesystem development at Oracle, Veritas, and contributions to OpenZFS. He holds a Masters in Computer Science from Penn State. Rohan serves as Industry Co-Chair for MSST, sits on the FMS Conference Advisory Board, reviews for ACM Transactions on Storage, and has served on the FAST and OSDI Artifact Evaluation Committees.

Shoaib Asif Qazi is a Ph.D. student at Virginia Tech, where he works on systems research with interests in operating systems, file systems, storage systems, memory management, and I/O optimization. His recent work focuses on emerging storage interfaces and disaggregated system design challenges, including SSD behavior and system software performance profiling.

Lisa Rivalin is a Systems Engineer on the Hardware Design team at Meta, where she has worked for six years. She applies data and AI methods to hardware engineering challenges. 

Currently, Lisa leads efforts to estimate and reduce the carbon footprint of Meta IT hardware inventory, and evaluates new server technologies to propose lower-impact designs. 

Previously at Meta, she led a digital twin initiative that combined physics-based modeling and machine learning to optimize data center design and operations.

Before Meta, Lisa was a research scientist at Engie, developing energy performance contracts and smart building technologies, and an affiliate research scientist at Lawrence Berkeley National Laboratory. She holds a PhD in Applied Statistics and Energy from Mines ParisTech, an MSc in Engineering from the University of Poitiers, and an MA in History and Philosophy of Science from Paris Diderot University.

Ronnie is a maintainer of libiscsi, libnfs and libsmb2. 

Harsha Vardhan Simhadri is a Partner Researcher at Microsoft Azure, where he focuses on algorithms and systems for large-scale vector search and unstructured data indexing. He is a co‑creator of DiskANN, a widely adopted approximate nearest neighbor search library that bridges the gap between research and production-scale deployments and is used across Microsoft and the broader industry. He is interested in developing practical and resource-efficient algorithms and machine learning systems for extreme scale systems, small and large. Harsha earned his PhD in Computer Science from Carnegie Mellon University. His work has been published at leading systems and machine learning venues, including NeurIPS, ICML, WWW, and VLDB, and has had significant impact on both research, benchmarks and production systems.

Kyuho Son is a Staff Software Engineer at Samsung Electronics. He specializes in disaggregated storage systems, NVMe over Fabrics, SPDK, and high-performance block I/O software. He has led key development efforts for Samsung’s PBSSD platform, including the design of a custom NVMe-oF data plane that significantly reduced write amplification. His interests include storage architecture, user-space drivers, distributed systems, and performance optimization.

Inho Song is a Ph.D. student in Computer Science at Virginia Tech. His research focuses on storage systems, with an emphasis on emerging SSD interfaces and architectures such as NVMe Flexible Data Placement (FDP) and Zoned Namespace (ZNS) SSDs. His work combines empirical characterization, systems design, and emulation to better understand device behavior and improve the interaction between storage hardware and software.

Ines Sousa is a Senior Sustainability Industry Advisor at Microsoft. Her work focuses on advancing industry-wide harmonization of actionable and scalable environmental impact assessment methodologies for Cloud IT hardware supply chain and driving strategic partnerships to accelerate decarbonization in the semiconductor industry. Prior to Microsoft, Ines led supply chain carbon footprinting, product life cycle assessment (LCA), supplier engagement and circularity initiatives at Google that were foundational for the company’s Net Zero supply chain strategy. She holds a Ph.D. from MIT in LCA for Product Design and a Master of Engineering in Environmental and Water Quality Engineering, also from MIT. She is an Environmental Engineer with a deep commitment to driving sustainability through data-driven, system-level innovation and collaboration.

Ross Stenfort is a Distinguished Engineer at SanDisk, driving storage innovation and industry collaboration.  He is an active collaborator with industry organizations including OCP, SNIA/SFF, and NVM Express.  Over his career, he has developed Storage Systems, SSDs, ROCs and HBAs and achieving 40+ patents. With 30+ years of experience across Meta, CNEX, Seagate, LSI, SandForce, SiliconStor, and Adaptec, Ross brings a broad and deep perspective on the storage ecosystem. He holds a B.S. in Electronic Engineering from Cal Poly, San Luis Obispo.

Himabindu Tummala is a Distinguished Engineer based in Hopkinton, Massachusetts, with deep expertise in large‑scale storage systems and distributed data architectures. Her work focuses on building AI‑ready data platforms, spanning data preparation and object‑based infrastructures that support modern analytics and AI workloads.

Carson Tunnell is a Staff Engineer in Sandisk's System Architecture team. He leads a systems validation environment used to evaluate and de‑risk emerging storage technologies, enabling early system‑level architectural exploration.

Wes Vaske is a Senior Member of Technical Staff at Micron Technology. As a Storage Solutions Architect with over 15 years of experience in data center storage systems, he is currently focused on developing high-performance NVMe solutions for AI workloads.

He has been a lead contributor to the MLPerf Storage Working Group helping to  define industry benchmarks for AI storage performance. Wes is a frequent presenter at Future of Memory and Storage (FMS) and SNIA Developer Conference (SDC) and Chairs the SNIA AI Data Workloads Technical Working Group (TWG)

Prior to his current role, Wes was a Systems Performance Engineer with the Data Center Workloads Engineering team for more than a decade, where he pioneered system observation, tracing, and analysis tools as well as developing automation frameworks enabling reproducible and insightful performance analysis across diverse environments that have become foundational to Micron’s workload-first product development strategy.

His earlier career includes performance engineering for Oracle RAC database systems at Dell Technologies.

Wes holds a B.S. in Physics from Iowa State University and continues to drive innovation at the intersection of storage, AI, and systems performance.

Zhe Wang builds highly durable, scalable, and secure storage layers for the modern cloud. As a Distinguished Engineer at Broadcom, he leads the storage layer for the Scalable Cloud File System, driving its native deployments across AWS, Azure, and GCP. With over 10 years of deep storage system experience, his career is defined by tackling complex data challenges. At Broadcom (which he joined via the Datrium acquisition), he developed the Ransomware Encryption Detection engine for their Ransomware Recovery solution and heavily contributed to the VLCR file system. At Datrium, he led the foundational storage pool and encryption layers. Zhe’s impact extends beyond traditional file systems; his Ph.D. research in Computer Science produced Multi-Probe LSH, a foundational technique that continues to power today's modern vector databases.

Rebecca is VP of Platform and Infrastructure Engineering at GEICO, leading their hybrid cloud transformation to repatriate key workloads, develop and deliver a true hybrid Open Source stack, and modernize their physical infrastructure. She recently led the organization that built, validated, and automated the full lifecycle management of Cloudflare’s compute, network, storage, and AI systems in 300+ cities and 100+ countries delivering >20% of the world’s Internet traffic. Rebecca is the former Open Compute Project President and Chairperson, helping ensure that hyperscale innovation can be scaled to all organizations, is on Fortune’s 40 Under 40 2020 list of most influential people in Technology, is on Business Insider's 2022 Cloudverse100 list of the builders of the next generation of the Internet, and was voted CloudGirls Trailblazer for women in technology in 2023. In her "spare" time, she is the lead singer of the funk and soul band, Sinister Dexter, and enjoys her passion of dance and choreography. She has two amazing little boys, and loves to run (after them, and on her own). Rebecca graduated from MIT with a degree in Computer Science and Electrical Engineering.