SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Jason Molgaard
Principal Storage Solutions Architect
Solidigm
Jason Molgaard has over 25 years of experience as a storage device controller RTL designer and architect having worked for various storage device companies architecting and designing HDD and SSD controllers. As a Principal Storage Solutions Architect on the Solidigm Pathfinding and Advanced Development Team, Jason focuses on future storage controller architectures and technologies, including Computational Storage and CXL. Jason is co-chair of the SNIA Computational Storage TWG and the SNIA Technical Council and is chair of the SDC agenda team. Jason was recognized by SNIA with an Exceptional Leadership award in 2020 and Volunteer of the Year award for 2023. Jason helps drive the Computational Storage standard at both SNIA and partner organizations including NVMe and OCP. Jason holds a Master of Science degree in Electrical Engineering.
Related Sessions
Can SDXI work with NVMe?
SDXI is an emerging standard for a memory data movement and acceleration interface. NVMe is an industry leading storage access protocol. Memory transfers are integral to storage access, including NVMe. Data is transferred by DMA from host memory to device memory or from device memory to host memory. With SDXI as the data mover, data movement is standardized and new transformation (compute) capabilities are enabled. Transparent memory data movement within and across storage nodes remains an active area of optimization for NVM subsystems. Leveraging SDXI as an industry standard technology within and across storage nodes for memory data movement and transformation is prudent and necessary for storage OEMs. The SNIA SDXI + CS subgroup will present standardizing data movement within NVMe, leveraging SDXI transformations to manipulate data in-flight, and an example flow for transparent data movement across storage nodes.
Host Addressing of NVMe Subsystem Local Memory
While a host has been able to address NVMe device memory using Controller Memory Buffer (CMB) and Persistent Memory Region (PMR), that memory has never been addressable by NVMe commands. NVMe introduced the Subsystem Local Memory IO Command Set (SLM), which allowed NVMe device memory to be addressable by NVMe commands; however, this memory could not be addressed by the host using host memory addresses. A new technical proposal is being developed by NVM Express that would allow SLM to be assigned to a host memory address range. We will describe the architecture of this new NVMe feature and discuss the benefits and use cases that host addressable SLM enables.
Computational Storage Architecture Simplification and Evolution
Computational Storage continues to gain interest and momentum as standards that underpin the technology mature. Developers are realizing that moving compute closer to the data is a logical solution to the ever-increasing storage capacities. Data-driven applications that benefit from database searches, data manipulation, and machine learning can perform better and be more scalable if developers add computation directly to storage.
Flexibility is key in the architecture of a Computational Storage device hardware and software implementation. Hardware flexibility minimizes development cost, controller cost, and controller power. Software flexibility leverages existing ecosystems and software stacks to simplify code development and facilitate workload deployment to the compute on the drive. Leveraging the hardware and software flexibility enables Computational Storage devices to deploy technologies available today, such as eBPF, while also providing a pathway to upcoming technologies like CXL and type 2 accelerators.
This presentation will show how to simplify computational storage architectures today and an evolutionary pathway to CXL. Attendees will walk away understanding how to reduce power, area, and complexity of their computational storage controller, leverage Linux and the Linux ecosystem of software to facilitate software development and workload management, and consider how new technologies may evolve computational storage capabilities.
The latest Efforts in the SNIA Computational Storage Technical Work Group (CS TWG)
With the ongoing work in the CS TWG, the chairs will present the latest updates from the membership of the working group. In addition, the latest release will be reviewed at a high level to provide attendees a view into next steps and implementation of the specification in progress. Use cases, Security considerations, and other key topics with also be addressed.
Standardizing Computational Storage
Computational Storage standards are under active development at both SNIA and NVMe. The CS TWG in SNIA continues to work on enhancements to the Architecture and Programming Model after the successful release of the 1.0 revision of the standard in August 2022. The CS TWG also continues to refine the CS API, which was released for public review in July 2022, to ensure alignment and compatibility with NVMe. Many of the same companies are engaged with the SNIA CS work and the NVMe CS work and strive to ensure compatibility and cohesion between the SNIA and NVMe CS standards. This presentation will discuss the current state of the SNIA CS Architecture and Programming Model, the current state of the CS API, and explain how these standards align with and support the NVMe CS efforts. Part of the discussion will include a lexicon of terminology from both standards and a decoder ring to translate between the slightly different terminology utilized between the two standards organizations.
Envisioning a Computational Storage Architecture with an SDXI Data Mover: Early Efforts
SDXI is a standard for a memory-to-memory data mover and acceleration interface that is extensible, forward-compatible, and independent of I/O interconnect technology. Among other features, SDXI standardizes an interface and architecture that can be abstracted or virtualized with a well-defined capability to quiesce, suspend, and resume the architectural state of a per-address-space data mover.
Computational Storage is a SNIA standard that defines architectures for offloading the host or reducing data movement. Compute resources residing on a storage device or very near a storage device perform computations on data instead of the host. Computational Storage reduces bandwidth and power requirements of the storage fabric and frees the host for other purposes.
While reducing data movement and offloading the host remains the goal, there are times when data needs to move to the compute or results need to move to the host. The SNIA SDXI+CS Subgroup is a new working group exploring the architectural possibilities of combining SDXI with Computational Storage. This presentation will share our current thinking and architectural explorations around unifying Computational Storage and SDXI as well as the use cases for SDXI-based Computational Storage devices.
