SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Scott is currently a Director of Strategic Planning at Solidigm. He has spent over 25 years in the semiconductor and storage space in MFG, Design, and Marketing. His experience spans 17 years at Micron. He spent time at STEC, where he was critical to the growth of the startup to acquisition. His efforts have helped lead to products in the market with over $300M in revenue. With over $2B in overall program revenues over the last 10 years. He recently spent time at NGD Systems driving Computational Storage Technology.
With the growth of Containerized applications and Kubernetes as an orchestration layer, the ability to leverage these technologies within the storage device directly adds additional support to the implementation and parallel processing of data. By using an os-based Computational Storage Drive (CSD), a deployment of SPARK will be presented and the steps required to achieve this task. The ability to use a distributed processing operation and orchestrate it with the Host and the CSDs at the same time to maximize the benefits of the application deployment.
In this presentation the Co-Chairs of the Computational Storage Technical Working Group (CS TWG) will provide a status update from the work having been done over the last year, including the release of the new Public Review materials around Architecture and APIs. We will update the status of the definition work and address the growing market and adoption of the technology with contributions from the 47+ member organizations participating in the efforts. We will show use cases, customer case studies, and efforts to continue to drove output from the Technical efforts.
Join the SNIA Computational Storage TWG and SIG for a Computational Storage update and discussion of the latest SNIA CS Architecture and Programming Model and API.
We will guide the group to discuss the 1.0 specification, what it means for the industry, and where we go from here.
Computational storage is a new paradigm in computing where data processing is moved closer to the storage device to enhance performance and reduce data transfer bottlenecks. In this presentation, we showcase how data integrity checks on CSDs with a software toolkit and a dedicated hardware to process the host payload can significantly improve storage performance and reduce data transfer overhead. This is a cross-industry effort that includes the system, the system software, and the CSD representing a complete end-to-end solution. We will compare the performance of the hardware-accelerated solution with traditional host software-based CRC calculations. We will also demonstrate the performance improvement achieved by hardware-accelerated data integrity checks on a CSD, and how this approach lends itself to easy scalability. Attendees will gain insight into how computational storage can be leveraged to reduce data transfer overhead and improve storage performance. This presentation will also highlight the benefits of using a software toolkit that abstracts the underlying hardware and enables easy integration of computational storage into existing storage architectures, and the advantage of adding HW acceleration capabilities at the device level.
In this BOF session, we will explore the need, opportunities, challenges and implications of emerging data compression techniques and accelerators associated with storage and memory technologies through diverse viewpoints of ecosystem participants, including an SOC Architect, technologists in the storage/memory device and controller space.
Join the conversation with Scott Shadley( Solidigm), Mats Oberg (Marvell), Pulkit Jain( AMD) , Angelos Arelakis (ZeroPoint Technologies).