SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Jim Handy
General Director
Objective Analysis
Jim Handy of Objective Analysis has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. A frequent presenter at trade shows, Mr. Handy is highly respected for his technical depth, accurate forecasts, widespread industry presence and volume of publication. He has written hundreds of market reports, articles for trade journals, and white papers, and is frequently interviewed and quoted in the electronics trade press and other media. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
Related Sessions
Chiplets, UCIe, Persistent Memory, and Heterogeneous Integration: The Processor Chip of the Future!
Chiplets have become a near-overnight success with today’s rapid-fire data center conversion to AI. But today’s integration of HBM DRAM with multiple SOC chiplets is only the very beginning of a larger trend in which multiple incompatible technologies will adopt heterogeneous integration to connect new memory technologies with advanced logic chips to provide both significant energy savings and vastly-improved performance at a reduced price point. In this presentation analysts Tom Coughlin and Jim Handy will explain how memory technologies like MRAM, ReRAM, FRAM, and even PCM will eventually displace the DRAM HBM stacks used with xPUs, on-chip NOR flash and SRAM, and even NAND flash in many applications. They will explain how DRAM’s refresh mechanism and NAND and NOR flash’s energy-hogging writes will give way to much cooler memories that will be easier to integrate within the processor’s package, how processor die sizes will dramatically shrink through the use of new memory technologies to replace on-chip NOR and SRAM, and how the UCIe interface will allow these memories to compete to bring down overall costs. They will also show how the approach will not only reduce the purchase price per teraflop, but also how the energy costs per teraflop will also improve.
Persistent Memories Without Optane, Where Would We Be?
Emerging memory technologies have gotten a couple of big boosts over the past few years, one in the form of Intel’s Optane products, and the other from the migration of CMOS logic to nodes that NOR flash, and now SRAM, cannot practically support. Although these appear to be two very different spheres, a lot of the work that has been undertaken to support Intel’s Optane products (also known as 3D XPoint) will lead to improved use of persistent memories on processors of all kinds: “xPUs”. In this presentation we will review emerging memory technologies and their roles in replacing other on-chip memories, the developments through SNIA and other organizations fostered by Optane, but usable in other aspects of computing, the emergence of new Near/Far Memory paradigms that have spawned interface protocols like CXL and OMI, and the emergence of “Chiplets,” and their potential role in the evolution of persistent processor caches.
Riding the Long Tail of Optane’s Comet - Emerging Memories, CXL, UCIe, and More
It’s been a year since the announcement that Intel would “Wind Down” its Optane 3D XPoint memories. Has anything risen to take its place? Should it? This presentation reviews the alternatives to Optane that are now available or are in development, and evaluates the likelihood that one or more of these could fill the void that is being left behind. We will also briefly review the legacy Optane left behind to see how that legacy is likely to be used to support persistent memories in more diverse applications, including cache memory chiplets. Along the way we’ll show how Optane not only spawned new thinking on software, as embodied in the SNIA Nonvolatile Memory Programming Model, but also drove the creation of new communication protocols, particularly CXL and UCIe.
Prepare for Fundamental Architectural Changes to Storage and Memory
Big changes lie ahead for the world of data processing in many areas: hardware structure, data management, processing algorithms, and even computing types (analog vs. digital.) How must the technical community prepare for these changes? Join noted analyst Jim Handy and IEEE President Tom Coughlin as they look at future computing systems in which storage will appear in new and interesting places. This session will examine how CXL might make persistent memory more widely available and bring processing closer to memory, while AI will drive both the broad adoption of new types of volatile DRAM in HBM stacks as well as the use of emerging nonvolatile technologies in AI-specific “Processing in Memory” (PIM) chips and embedded products for consumer and industrial applications. We’ll also show why computing is poised to convert to persistent caches, and eventually persistent register sets, either as memory on the processor chip or as chiplets, even though the DRAM that lies between persistent storage and persistent caches will remain volatile. We’ll touch on the evolution of “AI Everywhere” and show how altogether different approaches will be used for various applications, from neural networks at the edge and computational storage close to the source of the data, to massive centralized data centers that boast tens of thousands of GPUs, all the while explaining what architectures, software, and new algorithms will be needed to support this shift. These changes will require the development of new approaches to computing that will disrupt the fundamental direction of computing architecture.