SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Juan Orozco is a Platform Architect at Intel Data Center division. Juan was born and raised in Guadalajara, Jalisco, Mexico. He got his B.S. in Communications and Electronics Engineering in 2005 at the University of Guadalajara and his M. Eng. in Electronics Design at the Western Institute of Technology and Higher Education in 2013. Juan joined Intel in 2006 in the Advanced Platform Development team. He worked as PCB engineer, Hardware Design Engineer, and Design Lead on various Itanium and Xeon Server/Workstation Platforms. He transitioned in 2016 to the Data Center Platform Architecture division as Platform Architect, he is currently leading the next generation Xeon Server Reference Platform Architecture. Juan expertise are PCB Physical Design, hardware electrical design, digital design, Hardware and system architecture. He is passionate about playing with his kids, traveling around the world, puzzle building, playing soccer, and watching movies.
With the growing trend for PCIe and CXL solutions, there is a need to improve the sideband management path as currently defined using SMBus. The newest SNIA SFF-TA-1009 specification for EDSFF PCIe devices released in January 2023 defined a method to allow I3C upgrade of the management SMBus/I2C bus. Other standards organizations, such as OCP and PCI SIG, are looking into adopting the same design.
