SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
36-year veteran with most of that time focused on flash memory component and SSD design. He currently holds 60+ patents covering flash memory and security. He currently is a Fellow of Storage Solutions Architecture at Micron Technology.
As the rapid expansion of AI and analytics continues, storage system architecture and total cost of ownership (TCO) are undergoing significant transformation. Emerging technologies such as HAMR in rotating storage and high-capacity, data center-grade QLC in flash promise to redefine the landscape for both hyperscale and OEM data storage solutions. But what will that evolution look like? This panel brings together a distinguished group of industry experts to explore a wide range of perspectives—from hyperscaler and OEM viewpoints to strategic insights from both solid-state and rotating media technologists. Together, they will examine how shifting performance, density, and cost dynamics are reshaping storage architecture in an AI-driven future. Panel Lineup: * Madhavan Ravi – Hardware Systems Engineer, Meta. Designs and deploys storage hardware for exabyte-scale distributed systems. * Curtis Ballard – Distinguished Technologist, HPE. Focuses on storage architecture and next-generation technology strategy. * Currie Munce – Senior strategist for capacity storage architecture, Micron Technology; former Vice President. * Mohamad El-Batal – Chief Technologist, Cloud Systems Group, Seagate Technology. * Moderator: Steven Wells – Retired Fellow of SSD storage architecture (Intel, KIOXIA, and Micron).
The conflicting needs of datacenters managers hosting 3rd party and internal data securely and storage vendors needing to have a stream of vendor unique fleet telemetry for monitoring and debug has historically not found a scalable solution. This paper describes how a new proposal driven from the OCP Storage Workgroup facilitating standardized telemetry to be securely shared with storage vendors enabling vendor deep learning failure analysis and debug. The approach even allows vendor specific telemetry in a standard way vs current solutions such as NVMe SMART.
Should SSDs supporting power states higher than the maximum TDP dissipation supportable in a system? Many industry standards for drive form factors are targeting <=25W, but will Gen6 SSDs be viable in a x4 configuration or will these form factors be abandoned? What is proposed is a framework currently supported in NVMe and OCP's Datacenter NVMe SSD Specification of allowing enhanced latencies in cases where there is thermal margin above the maximum TDP of the form factor using either host orchestrated NVMe power state management or device orchestrated Host Controlled Thermal Management. The topic will also explore some enhanced terminology around thermal and electrical power limits to help facilitate the discussion.