SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Since the Enterprise and Datacenter Standard Form Factor (EDSFF) was created, the biggest complaint about EDSFF has been that there are too many form factors. While this was by design, EDSFF still has more form factors than what was supported previously in Enterprise and Datacenter application. So introducing E2 as a new EDSFF form factor in the market is obviously going to get a lot of scrutiny. The goal of this presentation is to discuss the motivation behind creating the EDSFF E2 form factor, why existing form factors could not meet this need, why the EDSFF E2 form factor ended up with the specific dimensions, and what do future applications look like.
The bandwidth and capacity demand explosion of AI are forcing interconnects and storage to rapidly adapt and evolve. Pushing the bandwidth challenges the limits of the copper interconnect. The SNIA SFF Technical Working Group is proactively addressing the bandwidth needs through new development work on 448G channel modeling and PCIe 7.0 projects as well as studying mechanical aspects of the system design. In addition, there is a focus on how to meet the capacity and performance needs of storage for AI through a new EDSFF form factor. Come ask our panel of experts questions to help better understand what is being done now to push these limits.
Since the Enterprise and Datacenter Standard Form Factor (EDSFF) was created, the biggest complaint about EDSFF has been that there are too many form factors. While this was by design, EDSFF still has more form factors than what was supported previously in Enterprise and Datacenter application. So introducing E2 as a new EDSFF form factor in the market is obviously going to get a lot of scrutiny.
The bandwidth and capacity demand explosion of AI are forcing interconnects and storage to rapidly adapt and evolve. Pushing the bandwidth challenges the limits of the copper interconnect. The SNIA SFF Technical Working Group is proactively addressing the bandwidth needs through new development work on 448G channel modeling and PCIe 7.0 projects as well as studying mechanical aspects of the system design. In addition, there is a focus on how to meet the capacity and performance needs of storage for AI through a new EDSFF form factor.
The SFF TA TWG within SNIA kicks out a bunch of specifications per year. But why should you care? Well, there is a very good chance your server has at least 1 SFF TA connector or cable or transceiver or device defined in it and likely many many more. As server technology changes, these components need to change for performance or size or thermals or to add functional capabilities. In this talk, the co-chairs of the SFF TA TWG will go through what detailed changes have been made to the specifications and what you need to care about.
With the growing trend for PCIe and CXL solutions, there is a need to improve the sideband management path as currently defined using SMBus. The newest SNIA SFF-TA-1009 specification for EDSFF PCIe devices released in January 2023 defined a method to allow I3C upgrade of the management SMBus/I2C bus. Other standards organizations, such as OCP and PCI SIG, are looking into adopting the same design.
AI is driving the need for more data movement between devices, boxes, and racks. This data transport requires higher bandwidths which puts strain on the interconnects as well as host and device designs. While you could tackle these problems on your own, instead come and ask questions of our expert panel from the SFF Technical Work Group to see if they can address your concerns. This will be an open Q&A where we want to hear your concerns so we can address them through industry aligned solutions.
