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SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA

Senior Director - NAND Product Planning - Standards,

Samsung

Mike Allison is a Sr. Director in the Samsung DSA Product Planning team focusing on standards for existing and future products. Mike is active in the many standards organizations that includes SNIA, NVM Express™, PCI Express™, DMTF, and OCP. He is the chair of the NVM Express Errata Task Group and the Representative on the OCP Steering Committee for the OCP Storage Project. He was the main author of the NVM Express TP4159 PCIe Infrastructure for Live Migration and TP4193 PCIe NVM Export Subsystem Migration which are associated with his presentation. For over 41 years, Mike has been an embedded firmware engineer and architect working on products for laser beam recorders, fighter aircraft, graphics cards, high end servers, and is now focusing on Solid State Drives. He holds 35 patents in graphics, servers, and storage. He has earned a BSEE/CS at University of Colorado, Boulder.

Solid State Storage Solutions

Host Management of NVM Express™ Exported NVM Subsystems in PCIe™ SSDs
Mike Allison
Mike Allison
Samsung
Lee Prewitt
Lee Prewitt
Microsoft
AI / ML

448G/lane? PCIe™ 7.0? E2 form factor? Suffer the egos of the opinionated experts working to meet the bandwidth, interconnect, and capacity for these AI capable interconnects and form factors.
Anthony Constantine
Anthony Constantine
Micron Technology
Mike Allison
Mike Allison
Samsung
John Geldman
John Geldman
KIOXIA

Host Management of NVM Express™ Exported NVM Subsystems in PCIe™ SSDs

Submitted by diegonika on
This presentation explains how an NVMe™ PCIe SSD supporting multiple NVMe controllers can be used to create and migrate virtual NVMe SSDs (i.e., Exported NVM Subsystems). The commands used by a host managing these virtual SSDs are fully illustrated using animation and demonstrates the interoperability between different SSD vendors during migration. Come and see how the virtual NVMe SSD is abstracted from the underlying NVMe SSD for the migrating Virtual Machine.

448G/lane? PCIe™ 7.0? E2 form factor? Suffer the egos of the opinionated experts working to meet the bandwidth, interconnect, and capacity for these AI capable interconnects and form factors.

Submitted by Anonymous (not verified) on

The bandwidth and capacity demand explosion of AI are forcing interconnects and storage to rapidly adapt and evolve.  Pushing the bandwidth challenges the limits of the copper interconnect. The SNIA SFF Technical Working Group is proactively addressing the bandwidth needs through new development work on 448G channel modeling and PCIe 7.0 projects as well as studying mechanical aspects of the system design.  In addition, there is a focus on how to meet the capacity and performance needs of storage for AI through a new EDSFF form factor.

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