SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Salon II
Thu Sep 21 | 9:10am
With the growing trend for PCIe and CXL solutions, there is a need to improve the sideband management path as currently defined using SMBus. The newest SNIA SFF-TA-1009 specification for EDSFF PCIe devices released in January 2023 defined a method to allow I3C upgrade of the management SMBus/I2C bus. Other standards organizations, such as OCP and PCI SIG, are looking into adopting the same design. OCP and PCI‑SIG agreed that a backward-compatible upgrade of SMBus was required (see Composable Security Architectures call to action at OCP Global Summit 2021, PCI SIG agreed to this in 2020).
We are presenting how important this upgrade is to solve the technical challenges that the new use cases create for SMBus architecture (example new use cases are MCTP protocol, SPDM-based attestation, telemetry reporting, or other asynchronous communications). We are showing how these challenges can be overcome by employing I3C-based solutions that have been designed from the very beginning with the new use cases in mind (the authors of this presentation co-authored the key specifications in this area: MIPI I3C, DMTF MCTP I3C Binding, I3C HUB design, NVMe-MI, EDSFF, and a newly proposed method to read VPD data over I3C). We are also showing how the I3C solution, which is backward-compatible with the legacy SMBus-only devices, actually improves operation of such legacy devices when they are attached to an I3C-capable system.
This paper presents the experimental results that validate the solution, including advanced topics such as polling mode, and includes the conclusions coming from the electrical and topology analysis. Intel and Solidigm partnered to implement the first I3C solution using off-the-shelf components from Aspeed, Renesas, and Microchip. This collaboration generated the experimental results demonstrating how SMBus fails to deliver the necessary functions and the value that comes with I3C upgrade.
The consumer video game software industry is on the cusp of its 50th year, and its revenues continue to grow steadily, in recent years outpacing even those of motion pictures. The role of data storage media is uniquely central to the video game industry, as it is ultimately the canvas upon which game developers paint. Despite the convenience of downloadable content via the Internet, strong demand continues for games on physical storage media, especially from major publishers.
Games from major publishers also require more storage than ever, not only for their distribution, but also for logging data about game play, from high score lists to saved session information and sharing playback videos. But the growth in the industry’s distribution media has slowed, from more than 1000 times over three generations of semiconductor ROM cartridges to hardly more than 150 times over five generations of optical discs. So what’s next?
This session reprises a popular 2019 SDC presentation surveying the significant roles and evolving types of digital storage media that enable this interactive digital art form, updated to include the latest generation of video game systems.
This is an update on the activities in the OCP Storage Project.
Enterprises are rushing to adopt AI inference solutions with RAG to solve business problems, but enthusiasm for the technology's potential is outpacing infrastructure readiness. It quickly becomes prohibitively expensive or even impossible to use more complex models and bigger RAG data sets due to the cost of memory. Using open-source software components and high-performance NVMe SSDs, we explore two different but related approaches for solving these challenges and unlocking new levels of scale: offloading model weights to storage using DeepSpeed, and offloading RAG data to storage using DiskANN. By combining these, we can achieve (a) more complex models running on GPUs that it was previously impossible to use, and (b) greater cost efficiency when using large amounts of RAG data. We'll talk through the approach, share benchmarking results, and show a demo of how the solution works in an example use case.
Chiplets have become a near-overnight success with today’s rapid-fire data center conversion to AI. But today’s integration of HBM DRAM with multiple SOC chiplets is only the very beginning of a larger trend in which multiple incompatible technologies will adopt heterogeneous integration to connect new memory technologies with advanced logic chips to provide both significant energy savings and vastly-improved performance at a reduced price point. In this presentation analysts Tom Coughlin and Jim Handy will explain how memory technologies like MRAM, ReRAM, FRAM, and even PCM will eventually displace the DRAM HBM stacks used with xPUs, on-chip NOR flash and SRAM, and even NAND flash in many applications. They will explain how DRAM’s refresh mechanism and NAND and NOR flash’s energy-hogging writes will give way to much cooler memories that will be easier to integrate within the processor’s package, how processor die sizes will dramatically shrink through the use of new memory technologies to replace on-chip NOR and SRAM, and how the UCIe interface will allow these memories to compete to bring down overall costs. They will also show how the approach will not only reduce the purchase price per teraflop, but also how the energy costs per teraflop will also improve.