Salon IV
Wed Sep 14 | 2:30pm
Large-scale data analytics, machine learning, and big data applications often require the storage of a massive amount of data. For cost-effective high bandwidth, many data centers have used tiered storage with warmer tiers made of flashes or persistent memory modules and cooler tiers provisioned with high-density rotational drives. While ultra fast data insertion and retrieval rates have been increasingly demonstrated by research communities and industry at warm storage, complex queries with predicates on multiple columns tend to still experience excessive delays when unordered, unindexed (or potentially only lightly indexed) data written in log-structured formats for high write bandwidth is subsequently read for ad-hoc analysis at row level. Queries run slowly because an entire dataset may have to be scanned in the absence of a full set of indexes on all columns. In the worst case, significant delays are experienced even when data is read from warm storage. A user sees even higher delays when data must be streamed from cool storage before analysis takes place. In this presentation, we present C2, a research collaboration between Seagate and Los Alamos National Lab (LANL) for the lab's next-generation campaign storage. Campaign is a scalable cool storage tier at LANL managed by MarFS that currently provides 60 PBs of storage space for longer-term data storage. Cost-effective data protection is done through multi-level erasure coding at both node level and rack level. To prevent users from always having to read back all data for complex queries, C2 enables direct data analytics at the storage layer by leveraging Seagate Kinetic Drives to asynchronously add indexes to data at per-drive level after data lands on the drives. Asynchronously constructed indexes cover all data columns and are read at query time by the drives to drastically reduce the amount of data that needs to be sent back to the querying client for result aggregation. Combining computational storage technologies with erasure coding based data protection schemes for rapid data analytics over cool storage presents unique challenges in which individual drives may not be able to see complete data records and may not deliver performance required by high-level data insertion, access, and protection workflows. We discuss those challenges in the talk, share our designs, and report early results.
Computational Storage
The growth of AI and large-scale analytics workloads has made data movement a primary bottleneck of modern storage systems.Near-Data Processing (NDP) addresses this by executing portions of the workload close to where the data resides.
The protocol-level fragmentation that historically blocked NDP adoption has now closed.The SNIA Computational Storage Architecture and Programming Model, the SNIA Computational Storage API, and the NVMe Computational Programs (CP) and Subsystem Local Memory (SLM) command sets — all three now ratified — together define the architecture model, host-side programming interface, and wire protocol for compute offload to storage targets.
The remaining barrier is stack fragmentation.They define the interface but do not deliver an integrated implementation: no documented end-to-end open implementation has combined a SNIA CS API host library, a CP/SLM transport layer, and an NVMe-oF target for the CP/SLM command sets.Without it, break-even goes unmeasured, deployments unvalidated, and future CSD silicon has no conformant reference.
We close this gap with a two-layer reference stack.The host layer exposes the SNIA CS API to applications; the target layer handles CP/SLM commands as an NVMe-oF Computational Storage target.NVMe wire protocol connects them; either layer is replaceable at the protocol boundary without changing the other.
The host layer, libcs, implements the SNIA CS API.Compute requests dispatch via xNVMe (extended with CP/SLM support) over NVMe-oF TCP; transport and target details stay behind a pluggable backend.
The target layer, SPDK CPCS, runs on a JBOF CPU over NVMe-oF TCP; no specialized CSD silicon required.A virtual dispatch layer routes execution to built-in, eBPF, or passthrough runtimes under a single NVMe wire protocol.
We characterize per-workload break-even across aggregation, filtering, vector similarity, and compression by sweeping buffer size, selectivity, dimensionality, and input entropy, identifying per-workload thresholds at which target-side offload outperforms host-side execution end-to-end.
Our contribution is the first publicly described end-to-end NVMe-CPCS stack: libcs and SPDK CPCS connected via xNVMe, integrated on commodity hardware. The per-workload break-even methodology is reusable by any conforming NVMe-CPCS target, including future CSD silicon, without modifying the application layer above libcs.
Computational Storage
High-performance SSDs use onboard DRAM for FTL tables and internal management with DRAM capacities increasing as SSD densities grow. As SSDs adopt newer DRAM technologies like DDR5, a large portion, often 40%-50%, of DRAM bandwidth remains underutilized by internal SSD operations. NVMe Controller Memory Buffer (CMB) and System Local Memory (SLM) features allow this unused DRAM bandwidth to be exposed to host applications. Leveraging CMB and SLM can unlock significant aggregate memory bandwidth across millions of SSDs in data centers, supporting high-performance workloads and new use cases. We'll discuss the architectural considerations and performance benefits of tapping into SSD DRAM bandwidth for enhanced resource efficiency in modern storage systems.
Computational Storage
After surveying large-scale AI and HPC workloads, we have identified a set of principles and best practices widely used in partitioning large sparse tensors and graphs for parallel execution. We present these in the context of a roadmap for standardization of both Data and Compute offload from costly and power-hungry memory and compute tiers to NDP (near data processing) devices. Our work on standardizing partitioning operators will improve the portability and performance of the programming interface and protocol between AI framework backends that emit large tensor operations and the most power-efficient computational memory and storage devices that implement processing elements as low as subarray level and can only handle smaller chunks of data.