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SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA

Fellow,

AMD

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding and has worked on some of the most complicated communication and storage solutions in the industry. He has a PhD from Edinburgh University.

Disrupting the GPU Hegemony: Can Smart Memory and Storage Redefine AI Infrastructure

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AI infrastructure is dominated by GPUs — but should it be? As foundational model inference scales, performance bottlenecks are shifting away from compute and toward memory and I/O. HBM sits underutilized, KVCache explodes, and model transfer times dominate pipeline latency. Meanwhile, compression, CXL fabrics, computational memory, and SmartNIC-enabled storage are emerging as powerful levers to close the tokens-per-second-per-watt gap.

NVMe Computational Storage Update

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Learn what is happening in NVMe to support Computational Storage devices. The development is ongoing and not finalized, but this presentation will describe the directions that the proposal is taking. Kim and Stephen will describe the high level architecture that is being defined in NVMe for Computational Storage. The architecture provides for programs based on a standardized eBPF. We will describe how this new command set fits within the NVMe I/O Command Set architecture. The commands that are necessary for Computational Storage will be described.

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