SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Now that NVMe™ has ratified TP4159 PCIe® Infrastructure for Live Migration, it is time to show the final details of how NVMe controllers in direct attached PCIe SSDs can be migrated from one server to the next for use cases such as workload balancing and maintenance. In this presentation I will detail the new commands, new events, new queues, updates to existing commands, and vendor specific options. This presentation will cover how a host utilizes the new protocol to migrate a controller. There will be example implementation options for the developed controllers supporting this new capability. Included will be error scenarios and the effects of resets.
If you write host software dealing with Virtual Machines, then this presentation is for you. If you are NVMe PCIe SSD supporting multiple NVMe controllers (i.e., multiple physical functions or SR-IOV), then this presentation is for you.
Oh, this new functionality can support other use cases for example Snapshotting, and maybe more.
Convey the details of the new test tools and methods to measure power consumption under traditional data center workloads, for systems and for devices.
Update attendees on regional regulatory bodies plans to adopt the SNIA Emerald specifications, US EPA, EU, and Japan.
Advise attendees how these specifications can be used within the supply chain, to augment Lifecycle Assessment disclosures, and related ESG report sections.
Large scale caching systems are making a transition from DRAM to SSDs for cost/power trade-offs and that brings out interesting challenges to both software and hardware. At Facebook, CacheLib is a widely deployed general purpose caching engine, enabling this transition through hybrid caching. In this talk, we introduce hybrid cache, highlight the challenges of hybrid caches at scale and the various techniques Facebook adopts to tackle these challenges. Looking forward CacheLib offers a platform for the software, hardware and academic community to collaborate on solving the upcoming challenges with new hardware and software solutions for caching. This talk is expected to take 30 minutes.
Boot Devices are a critical component of servers used at scale in the Data Center. The needs and use cases for boot drives in the Data Center are very different than client HDD and Flash based boot drives in laptop applications. This talk will describe the differences between client boot drive use cases and hyperscale use cases. This talk will describe hyperscale use-cases for boot drives, unique needs Hyper-Scalars have for flash based boot drives and hyperscale challenges when deploying flash based boot drives at-scale. This talk will also discuss pros and cons of various boot drive options for now and the future available to resolve these challenges.
As you know, the Storage Performance Development Kit (SPDK) provides a set of tools and libraries for writing high performance, scalable, user-mode storage applications. Kalray’s MPPA® manycore architecture proposes a unique 80-cores system.
A manycore processor is characterized by an apparent grouping from a software point of view of cores and their portion of the memory hierarchy into computing units. This grouping can delimit the scope of cache consistency and inter-core synchronization operations, include explicitly addressed local working memories (as opposed to caches), or even specific data movement engines and other accelerators. Computing units interact and access external memories and processor I/O through a communi¬cation device that can take the form of a network-on-chip (NoC).
The advantage of the manycore architecture is that a processor can scale to massive parallelism by replicating the computing units and extending the network on chip, whereas for a multi-core processor the replication applies to the core level. For storage purposes, the internal processor clusters are configured with one dedicated cluster as a control and management plane, and the remaining four clusters as four independent data planes.
We have implemented SPDK so that it provides a unique scalable platform that can deliver high performances on an 80-core system.This presentation will explain how we have ported SPDK on our processor core, and what unique pieces of technologies have been developed in order to coordinate with the processor internals. We will also explain how the platform can scale.
The conflicting needs of datacenters managers hosting 3rd party and internal data securely and storage vendors needing to have a stream of vendor unique fleet telemetry for monitoring and debug has historically not found a scalable solution. This paper describes how a new proposal driven from the OCP Storage Workgroup facilitating standardized telemetry to be securely shared with storage vendors enabling vendor deep learning failure analysis and debug. The approach even allows vendor specific telemetry in a standard way vs current solutions such as NVMe SMART.
Should SSDs supporting power states higher than the maximum TDP dissipation supportable in a system? Many industry standards for drive form factors are targeting <=25W, but will Gen6 SSDs be viable in a x4 configuration or will these form factors be abandoned? What is proposed is a framework currently supported in NVMe and OCP's Datacenter NVMe SSD Specification of allowing enhanced latencies in cases where there is thermal margin above the maximum TDP of the form factor using either host orchestrated NVMe power state management or device orchestrated Host Controlled Thermal Management. The topic will also explore some enhanced terminology around thermal and electrical power limits to help facilitate the discussion.
The EDSFF E3 form factors bring more options and commonality that enterprises and hyperscalers desire compared to traditional U.2, but also bring new challenges. With power envelopes increasing in many cases, it is difficult to fit more components on board to maximize capabilities. With a lack of E3 enclosures on the market, there many uncertainties like enclosure geometries and airflow profiles, and the uncertainty of total system power delivery capability. This presentation will explore the mitigations needed to pack in computational storage components in the E3 1T form factor and maintain thermal control within the constraints of the EDSFF E3 specs.