SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Data-Intensive Inference Done Better: Scaling Models and RAG in Limited Memory with SSD Offload
Abstract
Learning Objectives
The opportunities and challenges associated with AI inference with RAG The solution stack that enables offload of significant amounts of AI data from memory to SSD The impact of SSD offload to DRAM usage, QPS, index time, and recall The results of the SSD offload approach in an example use case (traffic video)
Related Sessions
OCP Storage Project Update
This is an update on the activities in the OCP Storage Project.
Data-Intensive Inference Done Better: Scaling Models and RAG in Limited Memory with SSD Offload
Enterprises are rushing to adopt AI inference solutions with RAG to solve business problems, but enthusiasm for the technology's potential is outpacing infrastructure readiness. It quickly becomes prohibitively expensive or even impossible to use more complex models and bigger RAG data sets due to the cost of memory. Using open-source software components and high-performance NVMe SSDs, we explore two different but related approaches for solving these challenges and unlocking new levels of scale: offloading model weights to storage using DeepSpeed, and offloading RAG data to storage using DiskANN. By combining these, we can achieve (a) more complex models running on GPUs that it was previously impossible to use, and (b) greater cost efficiency when using large amounts of RAG data. We'll talk through the approach, share benchmarking results, and show a demo of how the solution works in an example use case.
Chiplets, UCIe, Persistent Memory, and Heterogeneous Integration: The Processor Chip of the Future!
Chiplets have become a near-overnight success with today’s rapid-fire data center conversion to AI. But today’s integration of HBM DRAM with multiple SOC chiplets is only the very beginning of a larger trend in which multiple incompatible technologies will adopt heterogeneous integration to connect new memory technologies with advanced logic chips to provide both significant energy savings and vastly-improved performance at a reduced price point. In this presentation analysts Tom Coughlin and Jim Handy will explain how memory technologies like MRAM, ReRAM, FRAM, and even PCM will eventually displace the DRAM HBM stacks used with xPUs, on-chip NOR flash and SRAM, and even NAND flash in many applications. They will explain how DRAM’s refresh mechanism and NAND and NOR flash’s energy-hogging writes will give way to much cooler memories that will be easier to integrate within the processor’s package, how processor die sizes will dramatically shrink through the use of new memory technologies to replace on-chip NOR and SRAM, and how the UCIe interface will allow these memories to compete to bring down overall costs. They will also show how the approach will not only reduce the purchase price per teraflop, but also how the energy costs per teraflop will also improve.
