SDC: StorageAI™

Anthony Constantine is a Distinguished Member of Technical Staff responsible for Storage Standards at Micron. He is very active in SNIA as co-chair of the SFF TWG, an author for several EDSFF specifications, and author or contributor to several other SFF TWG specifications. He is also a past member of the SNIA Technical Council. In addition, Anthony contributes to PCI-SIG, JEDEC, NVMe, and Open Compute Platform (OCP). Anthony has over 25 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.

With nearly two decades of experience in storage systems architecture, I bring deep expertise spanning the complete evolution of storage technologies—from traditional HDDs, SCSI/iSCSI, and SATA through the NVMe revolution, including NVMeOF, ZNS, and Live Migration. My hands-on experience encompasses the entire storage stack: systems software development, SSD controller design and implementation, storage virtualization, distributed storage-networking architectures, and high-performance clustered file systems.
As an NVMe Upstream Kernel Co-Maintainer, my most significant contribution to the NVMe ecosystem has been spearheading the industry-wide standardization of NVMe Live Migration. I led the development of the NVMe Live Migration Research Paper (August 2022) through multi-vendor collaboration, presenting this work at SNIA SDC 2022 and subsequently driving the specification changes through both the upstream Linux Kernel community and NVMe TWG. This two-year effort was recognized with the FMS 2024 Most Innovative Memory Technology Award and resulted in successful integration into the NVMe specification.
As an integral member of NVIDIA's Storage Next initiative, I currently focus on extending NVMe capabilities to support the high-concurrency, fine-grained I/O requirements of GPU-initiated storage workloads. My work addresses how AI workloads are fundamentally transforming data center storage requirements, developing AI-centric architectures that integrate NVMe with accelerated computing platforms including SSDs, GPUs, DPUs, and IPUs. Through active engagement with storage fabric protocols and contributions to cross-industry technical working groups, I work to advance storage technology standardization and build the broad-based consensus essential for the future of storage-centric AI workloads.

Curtis Ballard is a Distinguished Technologist with Hewlett Packard Enterprise in the HPE Storage organization where he works on storage architecture, intellectual property, and storage technology strategy with a focus on enabling new storage technologies. Curtis has 30 years of experience in storage and storage interfaces technologies where he has worked in product design teams for storage arrays, storage enclosures, tape drives, tape libraries, and magneto optical drives. He has developed hardware designs for storage interfaces and storage controllers as well as firmware for motion control, storage interfaces, user interface, and embedded operating systems. In addition to Storage Platform development for HPE, Curtis also represents HPE in several industry organizations. Curtis is a treasurer for the NVM Express Board of Directors, is a member of the SNIA Technical Council, and is the vice-chair of the INCITS/SCSI (T10) Storage Interfaces Technical Committee where he has been the editor for several SCSI standards. He is an inventor on over 40 US patents in the storage industry across electrical, software, and mechanical disciplines.

Erich Haratsch is the Senior Director of Architecture at Marvell, where he leads the architecture definition of SSD and storage controllers.

Before joining Marvell, he worked at Seagate and LSI, focusing on SSD controllers.

Earlier in his career, he contributed to multiple generations of HDD controllers at LSI and Agere Systems.

Erich began his career at AT&T and Lucent Bell Labs, working on Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard.

He is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents.

A Senior Member of IEEE, Erich earned his MS and PhD degrees from the Technical University of Munich, Germany.

Gary Grider is the Leader of the High Performance Computing (HPC) Division at Los Alamos National Laboratory. Los Alamos’ HPC Division operates one of the largest governmental supercomputing centers in the world focused on US National Security for the US/DOE National Nuclear Security Administration.

As Division Leader, Gary is responsible for all aspects of High Performance Computing technologies and deployment at Los Alamos. Additionally, Gary is responsible for managing the R&D portfolio for keeping the new technology pipeline full to provide solutions to problems in the Lab’s HPC environment, through funding of university and industry partners. Gary has 30 granted patents in the data high performance data management area and has been working in HPC and HPC related storage since, 1984.

J is the Chair of SNIA’s Board of Directors and Technical Director for Systems Design for AMD where he works to coordinate and lead strategy on various industry initiatives related to systems architecture. Recognized as a leading storage networking expert, J is an evangelist for all storage-related technology and has a unique ability to dissect and explain complex concepts and strategies. He is passionate about the innerworkings and application of emerging technologies.

J has previously held roles in both startup and Fortune 100 companies as a Field CTO, R&D Engineer, Solutions Architect, and Systems Engineer. He has been a leader in several key industry standards groups, sitting on the Board of Directors for the Storage Networking Industry Association (SNIA), Fibre Channel Industry Association (FCIA), and Non-Volatile Memory Express (NVMe). A popular blogger and active on Twitter, his areas of expertise include NVMe, SANs, Fibre Channel, and computational storage.

J is an entertaining presenter and prolific writer. He has won multiple awards as a speaker and author, writing over 300 articles and giving presentations and webinars attended by over 10,000 people. He earned his PhD from the University of Georgia.

J. Mazzie received an M.S. in electrical engineering from West Virginia University (Morgantown, WV) in 2008. He is currently a Member of Technical Staff, Systems Performance Engineer, at Micron Technology, Inc. (2016-Present: TX, USA) and member of the SNIA Technical Council (Oct 2025-Present). John previously held roles at Dell, Inc. (Senior Storage Engineer) and WVHTC Foundation (Staff Engineer). He is currently focused on application performance analysis and tracing for AI workloads, as well as tool development.

Rory joined KIOXIA America in 2017. He has founded, built teams, and delivered product at four storage startups which were acquired ($400M, $165M and two undisclosed). Rory has more than twenty-five years of experience in data storage systems, data protection systems, and high performance computing with tenures as VP software Engineering at Samsung, Technical Director/CTO counsel at NetApp, CTO counsel at EMC, Vice President, Chief Storage Architect, and Distinguished Fellow at Quantum. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.

Simon A. F. Lund is a Principal Engineer at Samsung, where he leads the Systems Advancement and Integration (SAI) group and the Accelerator-integrated Storage I/O (AiSIO) project. His work focuses on system-software architectures that bridge compute and storage, informed by a background spanning storage systems engineering and research on high-performance compilers, runtime systems, and hardware architectures for massively parallel compute in array-oriented programming. He is also the lead developer of the open-source xNVMe project and holds a Ph.D. from the University of Copenhagen.

40+ year veteran with most of that time focused on flash memory component and SSD design. He holds 65+ patents covering flash memory and security. He is currently retired and enjoying contributing time and energy to the industry he's spent his entire adult life developing.

Ugur is a Distinguished Engineer in Dell’s Storage CTO organization, where she focuses on advancing storage technologies for modern AI workloads and building a robust, open AI ecosystem through strategic partnerships and active community engagement. She leads efforts to accelerate AI inference within the Dell AI Data Platform, driving innovations in storage connectors, protocols, data paths, and end‑to‑end I/O pipelines to meet the performance demands of large‑scale AI systems. Her work spans deep storage–compute integration and open‑source collaboration, ensuring that next‑generation storage platforms deliver highly scalable, low‑latency data access required for emerging AI workloads.

Wes Vaske is a Senior Member of Technical Staff at Micron Technology. As a Storage Solutions Architect with over 15 years of experience in data center storage systems, he is currently focused on developing high-performance NVMe solutions for AI workloads. He is a lead contributor to the MLPerf Storage Working Group, where he helps define industry benchmarks for AI storage performance. Wes is a frequent presenter at Future of Memory and Storage (FMS) and SNIA Developer Conference (SDC). Prior to his current role, Wes was a Systems Performance Engineer with the Data Center Workloads Engineering team for more than a decade, where he pioneered system observation, tracing, and analysis tools as well as developing automation frameworks enabling reproducible and insightful performance analysis across diverse environments that have become foundational to Micron’s workload-first product development strategy. His earlier career includes performance engineering for Oracle RAC database systems at Dell Technologies. Wes holds a B.S. in Physics from Iowa State University and continues to drive innovation at the intersection of storage, AI, and systems performance.

Alessandro Goncalves is a seasoned Storage Solutions Architect with deep expertise at the intersection of high-performance storage and AI/ML workloads. Currently at Solidigm, he architects and benchmarks SSD-based solutions tailored for emerging AI/ML pipelines, collaborating with industry consortia like MLCommons to drive next-generation storage standards. His background includes designing persistent memory solutions at Intel for Optane and accelerating performance tracing and debugging across hyperscaler environments. Alessandro’s recent work focuses on AI/ML storage integration, including workload-aware benchmarking, storage telemetry tooling, and scalable pipelines for data-centric AI systems.

Bill Lynn is an engineering Fellow at AMD.  Bill has over 40 years’ experience architecting and developing storage subsystems.  Bill started out as a disk drive designer with Digital Equipment Corporation designing 9”, 5.25”, 3.5” and 2.5” disk drives. Later he moved to Adaptec working in sales, marketing, and eventually the Office of the CTO as a RAID architect. During his tenure at Adaptec Bill helped form the SNIA IP Storage Forum and served as the forum chair for 2 years. Bill ran the early iSCSI interoperability events before transitioning the iSCSI interoperability effort to UNH. Bill was also one of the authors of the Infiniband specification. In 2006 Bill moved to Dell where he was responsible for server storage architecture. Bill was the original author of the SFF-8639 U.2 connector specification, one of the current editors of the SFF-TA-1008 EDSFF E3 device specification and served as Dell’s representative to the NVMe Board of Directors.  Bill moved to AMD in 2023 as part of AMD’s Data Center Architecture and Strategy group.

Jason is a Distinguished Engineer at Dell Technologies, working in the Storage Chief Technology Office. His role involves leading the development of next-generation storage and network protocols for both Public and Private Clouds. Jason also serves as Chair of the SNIA Accelerated Object I/O Technical Working Group. Throughout his career, Jason has focused on enterprise storage and meeting the needs of customers who want to expand beyond the traditional on-premises data center. He enjoys collaborating with customers and partners to understand their requirements when transforming their business. In his personal life, Jason is passionate about running marathons and baking artisan bread. He lives in Newton, Massachusetts, with his wife and their three children.

Chris J. Newburn, who goes by CJ, is a Distinguished Engineer who drives HPC strategy and the technical IO roadmap in NVIDIA GPU Cloud, focused on pushing the envelope for storage and networking programming models at scale, data center architecture and security, and scaled systems. He is a community builder with a passion for building an ecosystem that extends the core capabilities of hardware and software platforms from HPC into AI, data science, and visualization. He co-leads the Storage-Next effort to optimize products for IOPs/TCO. He tinkers with and leverages NVIDIA and vendor products in a lab packed with scaled compute, storage and networking gear to apply and extend new tech. He's delighted to have worked on volume products that his Mom used and that help researchers do their life's work in science that previously wasn't possible.

David L. Black, Ph.D. is a Senior Distinguished Engineer in the Infrastructure Systems Group Office of the CTIO at Dell Technologies, working primarily on storage and networking protocols and the integration of storage systems with server virtualization (e.g., VMware vSphere).  He was one of the original designers of both NVMe-over-Fabrics (NVMe-oF) and its TCP transport in addition to being one of the original designers of the iSCSI protocol.

Prior to joining EMC (which was subsequently merged with Dell), Dr. Black performed operating systems research and development at the Research Institute of the Open Software Foundation (OSF), which later became part of The Open Group.  He holds an M.S. and a Ph.D. in Computer Science from Carnegie Mellon University and an M.A. in Mathematics from the University of Pennsylvania.

Jason Duquette is a seasoned Platform Architect at Dell Technologies, where they serve as the Chief Platform Architect for Unstructured and Secondary Storage. Jason is also Co-Chair of the SNIA StorageAI Community. Previously, they held the title of Distinguished Engineer at Dell EMC, focusing on the PowerMax and PowerScale Storage Systems. Jason co-chaired the CXL Consortium from 2019 to 2023, contributing to the CXL/GenZ Bridge specification. They began their career as a Hardware Engineer at Mercury Computer Systems and have held various engineering and leadership roles across companies such as General Dynamics C4 Systems and Draeger Medical. Jason earned a BS in Electrical and Electronics Engineering from Worcester Polytechnic Institute.

Harsha Vardhan Simhadri is a Partner Researcher at Microsoft Azure, where he focuses on algorithms and systems for large-scale vector search and unstructured data indexing. He is a co‑creator of DiskANN, a widely adopted approximate nearest neighbor search library that bridges the gap between research and production-scale deployments and is used across Microsoft and the broader industry. He is interested in developing practical and resource-efficient algorithms and machine learning systems for extreme scale systems, small and large. Harsha earned his PhD in Computer Science from Carnegie Mellon University. His work has been published at leading systems and machine learning venues, including NeurIPS, ICML, WWW, and VLDB, and has had significant impact on both research, benchmarks and production systems.

Shrikant Mether is a Senior Principal Engineer with Hewlett Packard Enterprise (HPE) in the Storage organization. He holds M.S. in Information Networking from Carnegie Mellon University. Over past 13+ years, he has led various teams in storage control and data path. He currently leads the Storage Performance team at HPE with a special focus on storage for modern AI workloads.

Peter Corbett is a technology executive with over 30 years of experience in product research and development, currently serving as a Fellow, Storage System Architect at Dell Technologies. He holds a Ph.D. in Electrical Engineering from Princeton University and has previously held key roles at companies like HPE SimpliVity, IBM, and NetApp. As a member of the SNIA Board of Directors since 2021, Peter continues to drive advancements in storage technology.