Non-volatile Memory in the Storage Hierarchy: Opportunities and Challenges

New non-volatile memory technologies such as phase change memory and memristors are likely to result in an architectural redesign of the storage hierarchy in future computers. The ability to support a byte-addressable interface, access latencies comparable to DRAM, and high density will allow all or part of main memory to be non-volatile. Persistent storage will be much closer to the CPU and no translation between object and storage formats will be required. By virtually eliminating the performance gap between transient and persistent storage, this change has the potential to redefine the data persistence model used by applications. Data structures will be instantly persisted, preserved across system restarts, and available for reuse and sharing across applications.

However, there are significant challenges, from hardware issues such as endurance to software aspects such as data consistency. Processor caches and buffers between the CPU core and main memory will remain, allowing volatility in the system. If a program fails, persistent data may be incompletely updated or data invariants may not be satisfied. This talk will focus on software issues surrounding data consistency on non-volatile memory because of hardware or software failures. We will examine a few solution approaches, the tradeoffs involved, and the need for additional functionality in this regard.