Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. CXL technology is designed to address the growing needs of high-performance computational workloads by supporting heterogeneous processing and memory systems for applications in Artificial Intelligence, Machine Learning, communication systems, and High-Performance Computing.

Emergence of serial-attached protocols like CXL and OpenCAPI. It is possible to connect DRAM based devices in the same physical slot as NAND Flash SSD. This paper discusses which pieces of existing NVMe SSD standards, like Mechanical form-factors, management interface protocols, power mode and Thermal profiles, can be reused for DRAM based CXL Memory devices. This will not only save cost, but also accelerate the adoption because you can reuse existing software eco-system and extend it for managing any type of device, whether storage or memory.

With CXL, system software, system hardware, and applications software developers will soon be presented with opportunities to disaggregate and pool memory into a memory-as-a-service for multiple computing hosts. In this session, Charles Fan will describe the architecture of such a system, including both services transparent to the applications and APIs that allow deeper integration. The components that will be covered include (1) host-based transparent memory tiering; (2) fabric management that allows dynamic provisioning and sharing; (3) advanced data services.

There is a demand for Hierarchical memory as use cases demand higher amounts of memory capacity and bandwidth as AI/ML, database applications scale up and scale out. Software-Defined Memory (SDM) is an emerging HW-SW co-design architecture paradigm that provides software abstraction between applications and underlying memory resources with dynamic memory provisioning to achieve the desired SLA. With emergence of newer memory technologies and faster interconnects, it is possible to optimize memory resources deployed in cloud infrastructure while achieving best possible TCO.

This session will give a brief overview of CXL and its evolution and then focus on possible use cases for storage.

In order to develop open source CXL ecosystem software it has proven useful to emulate CXL features within the QEMU project. In this talk, I will introduce the current major CXL features that QEMU can emulate and walk you through how to set up a Linux + QEMU CXL environment that will enable testing and developing new CXL features. In addition, I will highlight some of the limitations of QEMU CXL emulation.

CXL is intended to interface to a wide variety of devices including memory and accelerators. CXL is certainly gaining momentum as a preferred interface for disaggregated memory while CXL accelerator devices are still in the early stages of development. Computational Storage is one example of an accelerator that is well positioned to achieve additional benefits from CXL. Data residing in Subsystem Local Memory (SLM) on an NVMe device could potentially be accessed with the load/store interface of CXL and maintain coherency with host memory.