Track Background Color
#000000
Old ID
14
Slack Channel Url
https://app.slack.com/client/T02DWHYB4P7/C02E5S99GJG

SNIA SDXI Roundtable: Towards Standardizing a Memory to Memory Data Movement and Acceleration Interface

Submitted by Anonymous (not verified) on

Smart Data Accelerator Interface (SDXI) is a proposed standard for a memory to memory data movement and acceleration interface. Software memcpy is the current data movement standard for software implementation due to stable CPU ISA. However, this takes away from application performance and incurs software overhead to provide context isolation. Offload DMA engines and their interface are vendor-specific and not standardized for user-level software.

InfiniBand/RoCE RDMA Specification Update

Submitted by Anonymous (not verified) on

The first phase of the IBTA Memory Placement Extensions (MPE), supporting low-latency RDMA access to persistent memory on Infiniband and RoCE networks, was published in August. In this talk, the MPE will be introduced, motivations for the additions discussed, and performance advantages of the MPE over current techniques will be reviewed. In addition to the these new MPE protocol enhancements in the new specification, additional operations, currently under development and planned for the next version, will also be presented.

Rethinking Software Defined Memory (SDM) for large-scale applications with faster interconnects and memory technologies

Submitted by Anonymous (not verified) on

Software-Defined Memory (SDM) is an emerging architecture paradigm that provides software abstraction between applications and underlying memory resources with dynamic memory provisioning to achieve the desired SLA. With emergence of newer memory technologies and faster interconnects, it is possible to optimize memory resources deployed in cloud infrastructure while achieving best possible TCO. SDM provides a mechanism to pool disjoint memory domains into a unified memory namespace.

Compute Express Link 2.0: A High-Performance Interconnect for Memory Pooling

Submitted by Anonymous (not verified) on

Data center architectures continue to evolve rapidly to support the ever-growing demands of emerging workloads such as artificial intelligence, machine learning and deep learning. Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices.

Enabling Heterogeneous Memory in Python

Submitted by Anonymous (not verified) on

Adopting new memory technologies such as Persistent Memory and CXL-attached Memory is a challenge for software. While libraries and frameworks (such as PMDK) can help developers build new software around emerging technology, legacy software faces a more severe challenge. At IBM Research Almaden we are exploring a new approach to managing heterogeneous memory in the context of Python. Our solution, PyMM, focuses on ease-of-use and is aimed primarily at the data science community. This talk will outline PyMM and discuss how it is being used to manage Intel Optane persistent memory.

PCIe® 6.0: A High-Performance Interconnect for Storage Networking Challenges

Submitted by Anonymous (not verified) on

Over the past nearly three decades, PCI-SIG® has delivered a succession of industry-leading specifications that remain ahead of the curve of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in diverse market segments, including data centers, PCs and automotive applications. Each new PCI Express® (PCIe®) specification consistently delivers enhanced performance, unprecedented speeds, and low latency – doubling the data rate over previous generations.

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