Accelerating Encryption for Solid State Storage Drives

A hardware accelerator to improve the throughput and power efficiency of encryption and decryption of solid state drive (SSD) based storage systems is presented. The accelerator interface takes advantage of the open source RISC-V ISA, which allows it to be attached to a RISC-V based microcontroller system-on-chip (SOC) in 2 different configurations, based on design time configuration. The accelerator presents a management interface which can be used to configure, start and stop operation, a completion interface which supports firmware polling or interrupts, and a memory interface through which it initiates I/O and memory accesses.

 

The accelerator can be attached inside a CPU in the tightly attached configuration, allowing firmware to use special register reads and writes for the management interface, polling or interrupts for the completion interface, and the CPU’s coherent memory subsystem for I/O or memory accesses. No additional RISC-V instructions are needed to operate the accelerator, only custom special register addresses. Alternatively, the accelerator can be attached to the SOC interconnect in the closely attached configuration, which allows it to participate in a coherency protocol, such as AXI or CHI, as a non-caching node. Memory mapped register reads and writes are used to configure the management interface, and I/O or memory read and write requests are initiated, and data fills and responses received via the memory interface. 

 

The accelerator adds support for separate processing threads, each of which can be allocated to separate storage devices, by providing a special register bank per thread which can be accessed via the management interface. Both design and run time configurability of the number of compute pipes associated with a thread are provided to allow reallocation of resources in a dynamic runtime environment. The number of channels in the memory interface is design time configurable to allow tuning of memory versus compute bandwidth for a particular system.The design is currently in development using Verilog, and is fully synthesizable to support soft IP integration into an SOC, or mapping to an FPGA. The goal is to support the most commonly used cryptographic protocols from TLS 1.3 including AES-128/256, SHA-256/512 as well as AES-GCM 128/256. The hardware accelerator can be used to improve throughput and power efficiency relative to firmware based solutions, which may be using the RISC-V crypto instruction set extensions (ISEs), running on the microcontroller.