Computational Storage is a new field that is addressing performance and scaling issues for compute with traditional server architectures. This is an active area of innovation in the industry where multiple device and solution providers are collaborating in defining this architecture while actively working to create new and exciting solutions. The SNIA Computational Storage TWG is leading the way with new interface definitions with Computational Storage APIs that work across different hardware architectures.

Computational Storage continues to gain interest and momentum as standards that underpin the technology mature. Developers are realizing that moving compute closer to the data is a logical solution to the ever-increasing storage capacities. Data-driven applications that benefit from database searches, data manipulation, and machine learning can perform better and be more scalable if developers add computation directly to storage.

NVMe and SNIA are both working on standards related to Computational Storage. The question that is continually asked is are these efforts are compatible or at odds with each other. The truth is that many of the same people are working on both of these standards efforts and are very interested in ensuring that they work together as opposed to conflicting with each other.

Large-scale data analytics, machine learning, and big data applications often require the storage of a massive amount of data. For cost-effective high bandwidth, many data centers have used tiered storage with warmer tiers made of flashes or persistent memory modules and cooler tiers provisioned with high-density rotational drives.

The exploration of computation near flash storage has been prompted by the advent of network-attached flash-based storage enclosures operating at tens of gigabytes/sec, server memory bandwidths struggling to keep up with network and aggregate I/O bandwidths, and the ever-growing need for massive data storage, management, manipulation and analysis. Multiple tasks from distributed analytical/indexing functions to data management tasks like compression, erasure encoding, and deduplication are all potentially more performant, efficient and economical when performed near storage devices.

Computational Storage offers near-data acceleration, and it is gaining popularity with recent commercialization and standardization efforts. In this talk, we present how Computational Storage can be used to scale the performance of a key-value storage engine and deep learning training workloads. We propose a new key-value storage engine, named RETINA, where Computational Storage, Samsung SmartSSD, accelerates its data processing and user-defined processing pipelines.

With the ongoing work in the CS TWG, the chairs will present the latest updates from the membership of the working group. In addition, the latest release will be reviewed at a high level to provide attendees a view into next steps and implementation of the specification in progress. Use cases, Security considerations, and other key topics with also be addressed.

Learn what is happening in NVMe to support Computational Storage devices. The development is ongoing and not finalized, but this presentation will describe the directions that the proposal is taking. Kim will describe the high level architecture that is being defined in NVMe for Computational Storage. We will describe how this new command set fits within the NVMe I/O Command Set architecture. The commands that are necessary for Computational Storage will be described. We will discuss a proposed new memory model that is able to be used for computational programs.

Data center systems power consumption is currently one of the biggest concern and green computing is main industry interest. Recent research found that more than 60% power is consumed in CPU in a server. SNIA and NVMe computational storage standard compliant Samsung Smart SSD achieves high energy-efficient computing by offloading computation from CPU to SSD. DB SCAN acceleration engine in Smart SSD demonstrated that it can internally process data at the full speed and highly enhance energy efficiency.

This presentation looks at a computational storage use-case within the Human Cell Atlas genomics research and discovers that the deployed HW CS engine is insufficient and why this is the case. The presentation shows the journey from standard system bench marking to micro-benchmarking specifically instruction per cycle analysis (IPC). This presentation also details the programming techniques used along the way, including intrinsic SIMD and inline assembler programming.