C+M+S Summit 2023 Speakers

George Apostol, CEO and Founder, Elastics.Cloud, Inc

George has over 35 years of experience designing system-on-chip (SoC), hardware, software, and systems. He holds several patents for interconnect and interface design and has led technology organizations developing products for several markets. He has held leadership and executive roles at Xerox/PARC, Sun, SGI, LSI Logic, Exar, and Samsung as well as start-ups including TiVo, BRECIS, Audience and BAYIS. As VP of Engineering and CTO at PLX Technology, George drove the development of PCI Express switches, which are broadly used in the market today. He received his bachelor’s degree in Electrical Engineering from the Massachusetts Institute of Technology.

JB Baker, Vice President, Marketing, ScaleFlux

JB Baker is a successful technology business leader with a track record of driving top and bottom line growth through new products for enterprise and data center storage.  He joined ScaleFlux in 2018 to lead Product Planning & Marketing as ScaleFlux expands the capabilities of computational storage and its adoption in the marketplace.

Sudhir Balasubramanian, Senior Staff Solution Architect and Global Oracle Practice Lead, VMware

Sudhir has been at VMware since 2012  as Senior Staff Solution Architect & Global Oracle Practice Lead. He has 27+ years Oracle hands-on experience.  His roles have included: Principal Oracle DBA / Architect, Oracle RAC/Data Guard Expert, experienced in  EMC SAN Technologies, Principal Oracle DBA/Oracle Architect (1995 – 2011) [Tata Consultancy Services (TCS), Sony Electronics, Newgen Results (Aspen) ,Teletech Corp, SAIC, Active Network, Sempra Energy Holdings]; VMware VCA – Cloud ,VMware vBCA Specialist, VMware vExpert; Member of the Office of the Chief Technical Ambassador VMware (Alumni); Oracle ACE.  He is the aeading author of “Virtualizing Oracle Business Critical Databases on VMware SDDC”.  Sudhir is a recognized Speaker at  Oracle Open World, IOUG, VMworld, VMware Partner Exchange, EMC World, EMC Oracle Summit and Webinars.

Andy Banta, Storage Janitor, Magnition

Andy has over 30 years of experience in high-tech industry giants. He worked on development teams at SCO, Sun Microsystems, VMware and NetApp-SolidFIre producing primarily storage and networking products. Andy is known for promoting simplicity and economy and has presented at numerous conferences, technology events and podcasts.

Outside of high tech, Andy is involved in auto racing, auto restoration and hiking. His interests include travel, wines and food.

Stephen Bates, VP, Huawei

Stephen is a VP and the Chief Architect of Emerging Storage Systems at Huawei. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.. Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.  He is a member of the SNIA Technical Council.

Kurtis Bowman, Marketing Working Group Co-Chair, CXL Consortium/Director, Server System Performance, AMD

Kurtis Bowman is the Marketing Working Group Co-Chair of the CXL Consortium and Director, Server System Performance at AMD. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in the technical and trade press.

Tom Coughlin, President, Coughlin Associates

Tom Coughlin is a digital storage analyst and business and technology consultant.  He has over 37 years in the data storage industry with engineering and management positions at several companies.  Coughlin Associates consults, publishes books and market and technology reports (including The Media and Entertainment Storage Report), and puts on digital storage-oriented events.  He is a regular storage and memory contributor for forbes.com and M&E organization websites.  Tom is an IEEE Fellow and President-Elect, and is active with SNIA and SMPTE. 

Clarete Riana Crasta, Master Technologist, Hewlett Packard Enterprise

Clarete Crasta is a Master Technologist at Hewlett Packard Enterprise. She has worked on a variety of projects and research topics including High Performance Computing, Operating Systems Kernel, Storage and Virtualization. Recently, she has been working on designing and building a software stack for Fabric Attached Memory system architecture. She has served as a member of the Technical Review Board and presented at multiple conferences. She also has patents and authored paper publications.

Dr. Debendra Das Sharma, Intel Senior Fellow and Chair of UCIe Consortium

Dr. Debendra Das Sharma is an Intel Senior Fellow and Director of I/O Technology and Standards Group. He is an expert in I/O subsystem and interface architecture, delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), coherency, multichip package interconnect, SoC, and rack scale architecture. He has been a lead contributor to multiple generations of PCI Express since its inception, a board member and leader of the PHY Logical group in PCI-SIG, and is the Chair of UCIe. Debendra joined Intel in 2001 from HP. He has a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst and a Bachelor of Technology (Hons) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur. He holds 99 U.S. patents and currently lives in Saratoga, Calif. with his wife and two sons. He enjoys reading and participating in various outdoor and volunteer activities with his family.

Sandeep Dattaprasad is a Senior Product Manager at Astera Labs with 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link™ products, SAS RAID controllers, SAS expanders and PCIe® switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep focuses on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using CXL technology.

Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Kelvin Goveas, Architect, Azimuth Technology

Kelvin Goveas is an architect at Azimuth Technolgy. He has 25+ years of experience in designing high performance CPUs which span the x86, ARM and RISC-V ISAs at AMD, ARM and Ventana Micro Systems respectively. Azimuth Technology was founded in August 2020 in Austin, Texas to contribute some of that experience into the design and development of hardware accelerator IP.

Pekon Gupta is leading the Strategic Business Development at Intel PSG’s Cloud and Enterprise Acceleration pision. He has been working to enable use of CXL in accelerators like DPU, IPU, and Computational Memory, taking CXL beyond simple memory expansion.

Before joining Intel, Pekon was working in System and Architecture roles at SMART Modular, Sandisk and Texas Instruments.

Vince Hache, Director Systems Architecture, Rambus

Vince Hache is a member of the CXL Consortium Technical Task Force and co-chair of both the Fabric Sub-Team and Manageability Sub-Team. His contributions to the CXL Specification include helping to define the Fabric Management API and Fabric Switch architecture. Mr. Haché has been providing architectural and engineering support for Tier 1 customer storage, server, and data center designs in the areas of NVMe and GPU interconnect, as well as Serial Attached SCSI (SAS) and PCIe infrastructure for more than ten years. Prior to the data center solutions industry, he worked in systems and software engineering for radar surveillance systems. He holds a Bachelor of Science degree in electrical engineering from Carleton University in Ottawa, Canada.

Jonmichael Hands partners with the storage vendors for Chia optimized product development, market modeling, and Chia blockchain integration. Jonmichael spent the last ten years at Intel in the Non-Volatile Memory Solutions group working on product line management, strategic planning, and technical marketing for the Intel data center SSDs. In addition, he served as the chair for NVM Express (NVMe), SNIA (Storage Networking Industry Association) SSD special interest group, and Open Compute Project for open storage hardware innovation. Jonmichael started his storage career at Sun Microsystems designing storage arrays (JBODs) and holds an electrical engineering degree from the Colorado School of Mines.

Jim Handy of Objective Analysis has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. A frequent presenter at trade shows, Mr. Handy is known for his technical depth, accurate forecasts, widespread industry presence and volume of publication. He has written hundreds of market reports, articles for trade journals, and white papers, and is frequently interviewed and quoted in the electronics trade press and other media. He posts blogs at www.TheMemoryGuy.com and http://www.TheSSDguy.com

Festus Hategekimana, Trusted Computing Group Work Group/SSD Security Architect, Solidigm

Festus Hategekimana is an SSD security architect at Solidigm and is currently serving in TCG Storage Workgroup as the editor of the TCG Key Per IO SSC specification. Festus holds a PhD in computer engineering from the University of Arkansas where he focused on developing systems security frameworks for enabling secure FPGA sharing in multi-tenants cloud systems

Eric Hibbard, Director, Product Planning - Storage Networking & Security, Samsung Semiconductor, Inc.

Eric A. Hibbard is the Director, Product Planning – Storage Networking & Security at Samsung Semiconductor, Inc. and a cybersecurity and privacy leader with extensive experience in industry (PrivSec Consulting LLC, Hitachi, Raytheon, Hughes, OAO Corp), U.S. Government (NASA, DoE, DoD), and academia (University of California). He has extensive exerperience architecting and auditing information and communications technology (ICT) infrastructures and solutions involving a wide range of technologies (IoT, cloud, storage, big data, AI, smart cities, blockchain) in organizations throughout the world.

Mr. Hibbard holds leadership positions in standards development organization and industry associations, including ISO/IEC, the InterNational Committee for Information Technology Standards (INCITS), the IEEE Computer Society, the American Bar Association (ABA), the Cloud Security Alliance (CSA), and the Storage Networking Industry Association (SNIA). Hibbard is or has served in an editorship role on the following international standards projects: ISO/IEC 22123 (Cloud computing – Vocabulary/Concepts), ISO/IEC 27031 (ICT readiness for business continuity), ISO/IEC 27050 (Electronic discovery), ISO/IEC 27040 (Storage security), ISO/IEC PAS 20648 (TLS for storage systems), Rec. ITU-T 3500 | ISO/IEC 17788 (Cloud computing -- Overview and vocabulary), and IEEE 1619-2018 (XTS-AES).

Mr. Hibbard possesses a unique set of professional credentials that include the (ISC)2 CISSP-ISSAP, ISSMP, and ISSEP certifications; IAPP CIPP/US and CIPT certifications; ISACA CISA and CDPSE certifications; and CSA CCSK certification. He has a BS in Computer Science.

Jonathan Hinkle, Distinguished Member of Technical Staff, Micron

Jonathan Hinkle is a Distinguished Member of Technical Staff in Micron’s Storage Business Unit. Previously, Jonathan was Executive Director and Distinguished Researcher of System Architecture at Lenovo, leading their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. pmcsJonathan also serves as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He has generated more than 34 granted or pending patents and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Shyam Iyer is the Chair for SDXI (Smart Data Acceleration Interface), a newly formed SNIA TWG, which aims to develop, extend and drive an extensible, virtualizable, forward-compatible, memory to memory data movement and acceleration interface standard. He is a Distinguished Engineer in Dell's Office of CTO for Servers with many years of experience researching, designing, developing, debugging, validating, leading and driving system and software solutions that have an industry wide impact.

Arvind Jagannath, Product Line Manager for vSphere Platform, VMware

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering from India.

Jianping (JP) Jiang is the VP of Product Marketing and Business Operation at Xconn Technologies, a silicon valley startup pioneering CXL switch IC. At Xconn, he is in charge of CXL ecosystem partner relationship, CXL product marketing, business development, corporate strategy and operations. Before joining Xconn, JP held various leadership positions at several large scale semiconductor companies, focusing on product planning/roadmaps, product marketing and business development. In these roles, he had been developing and executing competitive and differentiated product strategies, leading to successful product lines that generate over more than billions of dollars revenue annually. JP has a Ph.D degree in computer science from the Ohio State University.

Paul Kaler brings over 20 years of experience to his current role as the Future Storage Architect for ProLiant servers at Hewlett Packard Enterprise (HPE). He is responsible for researching and evaluating future storage and interconnect technologies and defining the server storage strategy for ProLiant servers. He has previously led development of SSD storage arrays, been founder and co-founder of a couple of startups, and helped develop the first dual-screen smartphone. Paul is also actively involved in multiple standards and industry organizations, and has been a key driver of standards including U.3, EDSFF E3, and the OCP Datacenter NVMe and SAS/SATA specs.

Tao Lu, Research Manager, DapuStor Corporation

Tao Lu received his Ph.D. degree in Electrical and Computer Engineering from Virginia Commonwealth University in 2016. He is the manager of the DapuStor research team in Shenzhen, China. He was previously a staff engineer at Marvell. His research interests include storage systems and architectures, virtualization and cloud computing, high performance computing, and computer system security. He has published many papers in major international journals and conferences such as TPDS, IPDPS, MSST, and INFOCOM.

Kim Malone, Storage Software Architect, Intel Corporation

Kim is a storage software architect at Intel Corporation, and has over 20 years of industry experience developing software for distributed high availability clustered systems for storage and networking products. Kim is engaged with computational storage standards initiatives with SNIA and NVMe, and is Co-Chair of the NVMe Computational Storage Task Group.

Dominic Manno is a research scientist with background in storage systems and software development focused in high performance computing. He is currently the file systems technical lead for the HPC pision at Los Alamos National Laboratory. This work includes leading design, development, and integration for HPC file systems deployed to support simulation science at LANL. Dominic also leads a subset of storage research efforts at LANL’s Ultrascale Systems Research Center where his work is focused on next generation storage systems for HPC datacenters. His most recent contributions include failure analysis impacting system design, metadata indexing, and computational storage research. He has contributed to multiple R&D100 winning entries including work on the Grand Unified File Index, a secure user metadata indexing system, and was part of a team that received a Government Innovation Award for computational storage work.

William Martin, SNIA Technical Council Co-Chair/Principal Engineer, SSD IO Standards, Samsung Semiconductor

Bill has been involved in the storage industry for over 35 years serving on industry consortiums and standards bodies for storage including SNIA, INCITS T10, INCITS T13, INCITS T11, SATA-IO, and NVMe. In addition to his role representing Samsung in SSD IO Standards, Bill currently holds the following industry leadership roles: co-chair of the SNIA Technical Council, Chair SNIA CMSI, Board member of the NVMe Board of Directors, Chair of INCITS T10, and Secretary of INCITS T13.

Bill is: editor of the SNIA Computational Storage Architecture Model; editor of the SNIA Computational Storage API; editor of the SNIA Key Value Storage API; editor of SCSI Block Commands – 5 (SBC-5); and author of numerous proposals to: NVMe, SNIA, INCITS T10, INCITS T13, and INCITS T11. He has received numerous industry recognitions for his contributions to the storage industry over the past decades including: SNIA Volunteer of the Year award 2021, INCITS Gene Milligan award for effective committee management 2016, INCITS Merit award 2013, FCIA Achievement award 2010, INCITS Outstanding Leadership Team award 2007, INCITS Technical Excellence award 2005, FCIA Lifetime Achievement award 2005, and SNIA Outstanding Theme lead for the interop lab 2004.

David McIntyre, Director, Product Planning and Business Enablement, Samsung Corporation

David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups.  He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.

As senior director of advanced product development, Andy Mills leads SMART Modular in developing and defining products in emerging technologies for AI, digital storage and other ascending technologies. Andy’s hands on experience in systems architecture, engineering, product strategy and development, technology roadmap formulation, and more gives SMART a leader with a true 360° perspective.

Jason Molgaard, Co-Chair, SNIA Computational Storage Technical Work Group/Principal Storage Solutions Architect, Solidigm

Jason Molgaard is an experienced storage controller architect having worked for various storage device companies architecting and designing HDD and SSD storage controllers. As a Principal Storage Solutions Architect on the Solidigm Pathfinding and Advanced Development Team, Jason focuses on future storage controller architectures and technologies, including Computational Storage and CXL. Jason is also co-chair of the SNIA Computational Storage TWG and helps drive the Computational Storage standard. Jason holds a Master of Science degree in Electrical Engineering and is a member of the SNIA Technical Council.

Aldrin Montana, PhD Student, University of California, Santa Cruz

Aldrin is currently a PhD student in computer science at UC Santa Cruz, advised by Peter Alvaro. His research interests include data management systems, storage systems, and bioinformatics.

Mats Öberg, Associate Vice President, Marvell

Mats Öberg is Associate Vice President, DSP Architecture, Office of the CTO, Storage and Memory Systems at Marvell. He leads research and development of signal processing for SSDs and HDDs. He also is responsible for computational storage and storage-related machine learning. Since joining Marvell, Mats has been leading the development of read channels for perpendicular recording and TDMR, as well optical recording for DVD and Blu-ray. Mats earned his PhD in Electrical Engineering from University of California, San Diego.

Jayasankar OP, Associate Technical Director, Samsung Electronics

Jayasankar OP is a technology enthusiast with 15+ industry experience in Servers & Storage domain. Major areas of work comprises SATA, SAS, NVMe, NVMeOF. At Samsung working as Validation Architect responsible for Client/Enterprise/DC drive products, Computational Storage and Samsung opensource initiatives.

Jake Oshins, Partner Software Engineer, Azure Core, Microsoft

Jake Oshins has spent his career at the intersection of hardware and software, defining and implementing industry standards like ACPI, UEFI, PCI and PCI Express.  He was an architect on the team that build Microsoft’s Hyper-V, which is one of Azure’s underpinning technologies.  Along the way, he was involved in the definition of SR-IOV and now he designs and builds hardware for Azure.

Arun V Pillai, Staff Engineer, Samsung Electronics

Arun is a professional with 8+ years of experience with technical contribution mainly in the field of test and development of Computational Storage, NVMe-oF controllers and All Flash Array reference designs, Proficient in automation using python, C++ and  storage testing.

Oscar Pinto, Principal Software Architect, Samsung Semiconductor

Oscar Pinto is a Principal Software Architect in the Memory Solutions Lab at Samsung Semiconductor Inc, California. He is a key contributor to the SNIA CS API definitions and works with a variety of innovate storage technologies in the NVMe/NVMe-oF space. His interests include storage architecture and interfaces, disaggregated and distributed environments. Oscar’s current responsibilities are in leading software architecture for Computational Storage and has 20+ years of industry experience in Operating Systems, device drivers and hardware definitions. He holds 25+ issued patents and has contributed to NVMe, NVMe-oF and RDMA Infiniband definitions and solutions.

Lee Prewitt is a Principal Hardware Program Manager with 25 years of storage industry experience ranging from Magneto-Optical to spinning rust to Flash. His former work at Microsoft has included working in the Windows and Devices Group where he was responsible for many of the components in the storage stack including File Systems, Spaces, Storport and Microsoft’s inbox miniport drivers. His responsibilities included storage devices ranging from SD and UFS in mobile to NVMe in Enterprise and Data Centers. He currently works in the Azure CSI team where he is responsible for future Data Center storage initiatives, specifications and evangelization.

Andy Rudoff, Principal Engineer, Intel

Andy Rudoff is a Senior Principal Engineer working in the area of storage and memory research in Intel Labs.  He is active in the CXL Consortium, helping define the HW/SW interfaces related to CXL memory devices.  He was a charter member of the SNIA NVM Programming Technical Work Group where he was instrumental in creating the PMem programming model now available in multiple operating systems.  Andy has more than 30 years experience in operating systems and storage.

Vishwas Saxena, Senior Technologist, Firmware Engineering, Western Digital

Vishwas is a Senior Technologist, Firmware Engineering at Western Digital, where he has conceptualized, architected and lead multiple products in emerging tech areas namely Machine Learning, Security, Blockchain, Networking, Wireless e.g. WD Crypto HW Wallet, Encrypted Content Search, wireless storage Drives, Edge Analytics based Video Surveillance Systems, Semantic image retrieval, and Flash Firmware products e.g NVMe-based CFexpress removable cards, CFast Cards.He has more than 14 years of experience in firmware development and almost 22 years of experience in the technology industry 

He earned a Masters in Machine Learning and AI (2011) from LJMU, Liverpool, UK and Bachelor’s in computer science (2000) from NSIT,Delhi,India.

Kapil Sethi is a Sr. Manager, New Business Product Planning at Samsung Semiconductor. At Samsung, he manages the CXL technology related product planning, new business exploration and ecosystem enablement.

Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.

Shreyas Shah, Founder and CTO, Elastics.cloud

Shreyas has over 25 years of progressive experience in the design of semiconductor, system design, and architecture in fields of computing, networking, storage technologies, virtualization and Flash based storage. He has held senior engineering positions at Alantec/FORE systems, Sisilk Networks, Fabric7 system, Founder at Xsigo system, Principal Data Center Architect at Xilinx & Intel and the Principal Architect at PLX. Shreyas received his Master's in Electrical, Specialization in Communications and Signal processing from IIT Bombay. Shreyas has over 15 patents issued and numerous pending.

Jim Shook, CISSP, CIPP/US, Global Director, Cybersecurity and Compliance Practice, Dell Data Protection

Jim combines his computer science degree and technical experience with over a decade as a litigator and general counsel, helping customers to better understand cybersecurity best practices and related regulatory and legal concerns. Today he focuses mainly on ransomware and destructive attacks, and combating their impact with cyber resilience capabilities and technologies.  Jim has led Dell's relationship with Sheltered Harbor and serves on its Joint Steering Committee. He is a long-time participant in and contributor to the Sedona Conference working groups on electronic information and cybersecurity and privacy.

Pradeep SR,Associate Technical Director, Samsung Semiconductor India Research 

Pradeep SR is an Associate Technical Director with extensive experience in the field of SSDs. He has spent 12 years in Samsung Semiconductor India Research (SSIR), working across Enterprise,DC,Client NVMe SSDs & SATA SSDs, with Firmware Verification & NVMe Protocol Compliance being the key focus areas, He is currently responsible for NVMe Client SSDs & innovation initiatives, and keen on Computational Storage & emerging SSD segments.

Paul Suhler is a member of the IEEE Security in Storage Work Group.

Ranjith T, Associate Staff Engineer, Samsung Semiconductor India Research

Ranjith Thottathil is currently working as an Associate Staff Engineer in Samsung Semiconductor India Research (SSIR).  Having completed a Masters in Embedded Systems, he has five years experience in SSD Firmware development and testing across SAS, SATA and NVMe Protocols. Ranjith has good knowledge and hands on experience in various SED protocols, and is currently responsible for Firmware verifcation on NVMe Client SSDs and SED protocol verification.

Andy Walls, Chief Architect, IBM Fellow, IBM Corporation

Andy Walls is Chief Architect and CTO for IBM’s Flash Systems pision. He is also an IBM Fellow, the company’s most prestigious honor. A 35-year storage industry veteran, Andy is a pioneer in enabling flash memory in the enterprise. He has developed enterprise storage systems that achieve high performance, good endurance, and the availability data centers require. He was responsible for the Texas Memory Systems acquisition and has since defined the architecture for all FlashSystem products. He is currently defining next generation products that can be used in traditional SAN environments as well as in clouds and by emerging workloads. He is widely recognized an expert in storage and flash memory. He has designed ASICs, PCBs, firmware stacks, and systems. Known as an innovator, he has filed over 100 patents. Andy earned a BSEE from UC Santa Barbara.

Chris Willman is a member of the IEEE Zero Trust Security Work Group.

 Steven Yuan, Founder and CEO, StorageX.ai

Steven has over 20 years of experience in the industry, beginning his career in the early days of flash memory and later becoming a senior architect for solid-state drives, storage systems, and data acceleration solutions. He has held various senior-level technical and leadership positions at Intel, Micron, and Western Digital, with his work spanning many aspects of enterprise and data center solutions on the memory, storage, SoC and system side. Over the past 20 years, his team has successfully delivered numerous products and launched them as comprehensive solutions for major data center players. Steven's experience and interests range from AI/ML, emerging memory, data center storage, and computing.

As the founder of StorageX.ai, his current focus is on transforming compute and storage architecture into a more sustainable system capable of addressing the challenges of rapidly growing data sizes, reduced application latency, and extreme demand for computing resources in various areas. Enabling data-centric computing is a key solution for this future world. Recently, he became the Co-chair of the SNIA DPU Special Interest Group (SIG).