High-speed optimized SPDK implementation on a 80 cores manycore processor

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Publish Date: 
Tuesday, June 8, 2021
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Abstract: 
As you know, the Storage Performance Development Kit (SPDK) provides a set of tools and 
libraries for writing high performance, scalable, user-mode storage applications. 
 
Kalray’s MPPA® manycore architecture proposes a unique 80-cores system.
 
A manycore processor is characterized by an apparent grouping from a software point of view of cores 
and their portion of the memory hierarchy into computing units. This grouping can delimit the scope 
of cache consistency and inter-core synchronization operations, include explicitly addressed local working 
memories (as opposed to caches), or even specific data movement engines and other accelerators.
Computing units interact and access external memories and processor I/O through a communi¬cation device that 
can take the form of a network-on-chip (NoC).
The advantage of the manycore architecture is that a processor can scale to massive parallelism by replicating 
the computing units and extending the network on chip, whereas for a multi-core processor the replication 
applies to the core level.
 
For storage purposes, the internal processor clusters are configured with one dedicated cluster as a control 
and management plane, and the remaining four clusters as four independent data planes. 
We have implemented SPDK so that it provides a unique scalable platform that can deliver 
high performances on an 80-core system.
This presentation will explain how we have ported SPDK on our processor core, and what unique pieces of
technologies have been developed in order to coordinate with the processor internals.
We will also explain how the platform can scale.
 
 

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