Smart Data Accelerator Interface Technical Work

The SDXI TWG -

• Develops and standardizes an extensible, forward-compatible memory to memory data mover interface that is independent of actual data mover implementations and underlying I/O interconnect technology. A PCIe device model is described. The interface can be extended to other device models.
• Proposed standard supports-
  • Data movement between different address spaces including user address spaces located within different virtual machines
  • Data movement without mediation by privileged software once a connection has been established.
  • An interface and architecture that can be abstracted or virtualized by privileged software to allow greater compatibility of workloads or virtual machines across different servers.
  • A well-defined capability to quiesce, suspend, and resume the architectural state of a per-address-space data mover to allow “live” workload or virtual machine migration between servers.
  • Mechanisms to enable forwards and backwards compatibility across future specification revisions. Allows software and hardware designed to different specification revisions to interoperate.
  • Ability to incorporate additional offloads in the future leveraging the architectural interface.
  • Concurrent DMA model.
• Coordinates the submission of new feature proposals to standards groups like PCISIG, CXL, OFA, UEFI, Gen-Z etc.

Version 1.0 of the Smart Data Accelerator Interface Specification has been released. 

Watch the video to learn about the specification, and also check out an interview with Shyam Iyer, SDXI Technical Work Group Chair, at Flash Memory Summit.

As new memory technologies get adopted and memory fabrics expand the use of tiered memory, data mover acceleration and its uses will increase. This TWG will encourage adoption and extensions to this data mover interface.