The popular xPU webcast series hosted by the SNIA Networking Storage Forum’s continued last month with an in-depth look at accelerator offload functions of the xPU. Our experts discussed the problems the xPUs solve, where in the system they live, and the functions they implement. If you missed the session, you can watch it on-demand and access the presentation slides at the SNIA Educational Library. The Q&A here offers additional insights into the role of the xPU. Q. Since xPUs can see traffic on the host doesn’t that widen the surface area for exposure if it were to be compromised? A. There is another aspect of this question: It depends on who owns control of the device and who’s allowed to run software there. If the organization that runs the infrastructure owns the xPU and controls the software that goes on there, then it can act as a security boundary to the rest of the host which might be running user software or other kinds of software. So, you can use the xPU as a security check in a security boundary and it actually could reduce the total attack surface or provide better security isolation. If you open up the xPU to be just another general-purpose micro server, then it has effectively the same attack surface as the hosting system, but you could run it in a mode or control it in a mode where it actually reduced the total attack service and make that a security boundary. That’s one of the interesting notions that’s come out in the industry on how xPUs can provide value. Q. Before, the host internal-only traffic was only exposed if the host was compromised, but now if the xPU is compromised it might exfiltrate information without the host being aware. Cuts both ways – I get that it is a hardened domain…. but everything gets compromised eventually.   A. Any programmable offload engine or hypervisor in a deployment has this same consideration. The xPU is most similar to a hypervisor that is providing common services such as storage or packet forwarding (vswitch) to its VMs. See the previous answer for additional discussion. Q. What are the specific offloads and functions that xPUs offer that NICs and HBAs don’t provide today? A. From a storage offloads point of view, in addition to the data path offloads, the xPU has the integrated SOC CPU cores. Portions of the storage stack or the whole storage application and the control plane could be moved to the xPU. The addition of accessible CPU cores, programmable pipelines, and directly usable offload engines, coupled to a general-purpose operating system, make the xPU fundamentally different from previous standard NIC- or HBA-based offloads. For the xPU, we’re now talking about the infrastructure services offloads with storage applications as one of the key use cases. For that reason, we have this new xPU terminology which describes this new type of device that offloads infrastructure services of the hypervisor functionality. With xPUs, the host CPU cores can be completely freed up for hosting customer applications, containers, and VMs. NICs and HBAs typically offload only specific network or storage functions. xPUs can run an expanded set of agents, data services or applications. To summarize at a high-level, you have local switching both on the PCIe side and on the network side, together with general purpose processors, plus the degree of programmability of the accelerators and the flexibility in the ways you can use an xPU. Q. When security offload is enabled, do we still need single flow 100G rate? Can you talk about use cases and where it may be needed? A. If the application or workload needs 100G line rate (or any other single flow specific rate) encryption and integrity, you need to find a specific xPU model that supports the desired security offload rate. xPU models will have varying capabilities. Typical workloads which might require this scale of single flow rate include storage access across a local network, AI workloads, technical computing, video processing, and large-scale streaming. Q. When will you be hosting the next xPU webcast? A. We’re glad you asked! The third presentation in this series will be “xPU Deployment and Solutions Deep Dive” on August 24, 2022 where we will explain key considerations on when, where and how to deploy xPUs. You can register here.

The SNIA Networking Storage Forum kicked off its xPU webcast series last month with “SmartNICs to xPUs – Why is the Use of Accelerators Accelerating?” where SNIA experts defined what xPUs are, explained how they can accelerate offload functions, and cleared up confusion on many other names associated with xPUs such as SmartNIC, DPU, IPU, APU, NAPU. The webcast was highly-rated by our audience and already has more than 1,300 views. If you missed it, you can watch it on-demand and download a copy of the presentation slides at the SNIA Educational Library.

The live audience asked some interesting questions and here are answers from our presenters.

Q. How can we have redundancy on an xPU?

A. xPUs are optimal for optimizing and offloading server/appliance and application redundancy schemes. Being the heart of the data movement and processing at the server, xPUs can expose parallel data-paths and be a reliable control point for server management. Also, the xPUs’ fabric connecting the hosts can provide self-redundancy and elasticity such that redundancy between xPU devices can be seamless and provide simplified redundancy and availability scheme between the different entities in the xPU fabric that is connecting between the servers over the network. The fact that xPUs don’t run the user applications, (or maybe in the worst case run some offload functions for them) makes them a true stable and reliable control point for such redundancy schemes. It’s also possible to put two (or potentially more) xPUs into each server to provide redundancy at the xPU level.

Q. More of a comment.  I'm in the SSD space, and with the ramp up in E.1L/S E.3 space is being optimized for these SmartNICs/GPUs, DPUs, etc.  Also better utilizing space inside a server/node, and allow for serial interface location on the PCB.  Great discussion today.

A. Yes, it’s great to see servers and component devices evolving towards supporting cloud-ready architectures and composable infrastructure for data centers. We anticipate that xPUs will evolve into a variety of physical form factors within the server especially with the modular server component standardization work that is going on. We’re glad you enjoyed the session.

Q. How does CXL impact xPUs and their communication with other components such as DRAM? Will this eliminate DDR and not TCP/IP?   

A. xPUs might use CXL as an enhanced interface to the host, to local devices connected to the xPU or to a CXL fabric that acts as an extension of local devices and xPUs network, for example connected to an entity like a shared memory pool. CXL can provide an enhanced, coherent memory interface and can take a role in extending access to slower tiers of memory to the host or devices through the CXL.MEM interface. It can also provide a coherent interface through the CXL.CACHE interface that can create an extended compute interface and allow close interaction between host and devices. We think CXL will provide an additional tier for memory and compute that will be living side by side with current tiers of compute and memory, each having its own merit in different compute scenarios. Will CXL eliminate DDR? Local DDR for the CPU will always have a latency advantage and will provide better compute in some use cases, so CXL memory will add additional tiers of memory/PMEM/storage in addition to that provided by DDR.  

Q. Isn't a Fibre Channel (FC) HBA very similar to a DPU, but for FC?

A. The NVMe-oF offloads make the xPU equivalent to an FC HBA, but the xPU can also host additional offloads and services at the same time. Both FC HBAs and xPUs typically accelerate and offload storage networking connections and can enable some amount of remote management. They may also offload storage encryption tasks. However, xPUs typically support general networking and might also support storage tasks, while FC HBAs always support Fibre Channel storage tasks and rarely support any non-storage functions.

Q. Were the old TCP Offload Engine (TOE) cards from Adaptec many years ago considered xPU devices, that were used for iSCSI?

A.They were not considered xPUs as—like FC HBAs—they only offloaded storage networking traffic, in this case for iSCSI traffic over TCP. In addition, the terms “xPU,” “IPU” and “DPU” were not in use at that time. However, TOE and equivalent cards laid the ground work for the evolution to the modern xPU.

Q. For xPU sales to grow dramatically won't that happen after CXL has a large footprint in data centers?

A. The CXL market is focused on a coherent device and memory extension connection to the host, while the xPU market is focused on devices that handle data movement and processing offload for the host connected over networks. As such, CXL and xPU markets are complementary. Each market has its own segment and use case and viability independent on each other. As discussed above, the technical solutions are complements so that the evolution of each market proliferates from the other. Broader adoption of CXL will enable faster and broader functionality for xPUs, but is not required for rapid growth of the xPU market.

Q. What role will CXL play in these disaggregated data centers?

A. The ultimate future of CXL is a little hard to predict. CXL has a potential role in disaggregation of coherent devices and memory pools at the chassis/rack scale level with CXL switch devices, while xPUs have the role of disaggregating at the rack/datacenter level. xPUs will start out connecting multiple servers across multiple racks then extend across the entire data center and potentially across multiple data centers (and potentially from cloud to edge). It is likely that CXL will start out connecting devices within a server then possibly extend across a rack and eventually across multiple racks. 

If you are interested in learning more about xPUs, I encourage you to register for our second webcast

“xPU Accelerator Offload Functions”to hear what problems the xPUs are coming to solve, where in the system they live, and the functions they implement.

The SNIA Networking Storage Forum kicked off its xPU webcast series last month with “SmartNICs to xPUs – Why is the Use of Accelerators Accelerating?” where SNIA experts defined what xPUs are, explained how they can accelerate offload functions, and cleared up confusion on many other names associated with xPUs such as SmartNIC, DPU, IPU, APU, NAPU. The webcast was highly-rated by our audience and already has more than 1,300 views. If you missed it, you can watch it on-demand and download a copy of the presentation slides at the SNIA Educational Library. The live audience asked some interesting questions and here are answers from our presenters. Q. How can we have redundancy on an xPU? A. xPUs are optimal for optimizing and offloading server/appliance and application redundancy schemes. Being the heart of the data movement and processing at the server, xPUs can expose parallel data-paths and be a reliable control point for server management. Also, the xPUs’ fabric connecting the hosts can provide self-redundancy and elasticity such that redundancy between xPU devices can be seamless and provide simplified redundancy and availability scheme between the different entities in the xPU fabric that is connecting between the servers over the network. The fact that xPUs don’t run the user applications, (or maybe in the worst case run some offload functions for them) makes them a true stable and reliable control point for such redundancy schemes. It’s also possible to put two (or potentially more) xPUs into each server to provide redundancy at the xPU level. Q. More of a comment. I’m in the SSD space, and with the ramp up in E.1L/S E.3 space is being optimized for these SmartNICs/GPUs, DPUs, etc. Also better utilizing space inside a server/node, and allow for serial interface location on the PCB.  Great discussion today. A. Yes, it’s great to see servers and component devices evolving towards supporting cloud-ready architectures and composable infrastructure for data centers. We anticipate that xPUs will evolve into a variety of physical form factors within the server especially with the modular server component standardization work that is going on. We’re glad you enjoyed the session. Q. How does CXL impact xPUs and their communication with other components such as DRAM? Will this eliminate DDR and not TCP/IP?    A. xPUs might use CXL as an enhanced interface to the host, to local devices connected to the xPU or to a CXL fabric that acts as an extension of local devices and xPUs network, for example connected to an entity like a shared memory pool. CXL can provide an enhanced, coherent memory interface and can take a role in extending access to slower tiers of memory to the host or devices through the CXL.MEM interface. It can also provide a coherent interface through the CXL.CACHE interface that can create an extended compute interface and allow close interaction between host and devices. We think CXL will provide an additional tier for memory and compute that will be living side by side with current tiers of compute and memory, each having its own merit in different compute scenarios. Will CXL eliminate DDR? Local DDR for the CPU will always have a latency advantage and will provide better compute in some use cases, so CXL memory will add additional tiers of memory/PMEM/storage in addition to that provided by DDR. Q. Isn’t a Fibre Channel (FC) HBA very similar to a DPU, but for FC? A. The NVMe-oF offloads make the xPU equivalent to an FC HBA, but the xPU can also host additional offloads and services at the same time. Both FC HBAs and xPUs typically accelerate and offload storage networking connections and can enable some amount of remote management. They may also offload storage encryption tasks. However, xPUs typically support general networking and might also support storage tasks, while FC HBAs always support Fibre Channel storage tasks and rarely support any non-storage functions. Q. Were the old TCP Offload Engine (TOE) cards from Adaptec many years ago considered xPU devices, that were used for iSCSI? A.They were not considered xPUs as—like FC HBAs—they only offloaded storage networking traffic, in this case for iSCSI traffic over TCP. In addition, the terms “xPU,” “IPU” and “DPU” were not in use at that time. However, TOE and equivalent cards laid the ground work for the evolution to the modern xPU. Q. For xPU sales to grow dramatically won’t that happen after CXL has a large footprint in data centers? A. The CXL market is focused on a coherent device and memory extension connection to the host, while the xPU market is focused on devices that handle data movement and processing offload for the host connected over networks. As such, CXL and xPU markets are complementary. Each market has its own segment and use case and viability independent on each other. As discussed above, the technical solutions are complements so that the evolution of each market proliferates from the other. Broader adoption of CXL will enable faster and broader functionality for xPUs, but is not required for rapid growth of the xPU market. Q. What role will CXL play in these disaggregated data centers? A. The ultimate future of CXL is a little hard to predict. CXL has a potential role in disaggregation of coherent devices and memory pools at the chassis/rack scale level with CXL switch devices, while xPUs have the role of disaggregating at the rack/datacenter level. xPUs will start out connecting multiple servers across multiple racks then extend across the entire data center and potentially across multiple data centers (and potentially from cloud to edge). It is likely that CXL will start out connecting devices within a server then possibly extend across a rack and eventually across multiple racks. If you are interested in learning more about xPUs, I encourage you to register for our second webcast “xPU Accelerator Offload Functions”to hear what problems the xPUs are coming to solve, where in the system they live, and the functions they implement.

Last month’s SNIA Persistent Memory and Computational Storage Summit (PM+CS Summit) put on a great show with 35 technology presentations from 41 speakers. Every presentation is now available online with a video and PDF found at www.snia.org/pm-summit.

Recently, SNIA On Storage sat down with David McIntyre, Summit Chair from Samsung, on his impressions of this 10^th annual event.

SNIA On Storage (SOS): What were your thoughts on key topics coming into the Summit and did they change based on the presentations? David McIntyre (DM): We were excited to attract technology leaders to speak on the state of computational storage and persistent memory.  Both mainstage and breakout speakers did a good job of encapsulating and summarizing what is happening today.  Through the different talks, we learned more about infrastructure deployments supporting underlying applications and use cases. A new area where attendees gained insight was computational memory. I find it encouraging that as an industry we are moving forward on focusing on applications and use cases, and supporting software and infrastructure that resides across persistent memory and computational storage.  And with computational memory, we are now getting more into the system infrastructure concerns and making these technologies more accessible to application developers. SOS: Any sessions you want to recommend to viewers? DM: We had great feedback on our speakers during the live event.  Several sessions I might recommend are Gary Grider of Los Alamos National Labs (LANL), who explained how computational storage is being deployed across his lab; Chris Petersen of Meta, who took an infrastructure view on considerations for persistent memory and computational storage; and Andy Walls of IBM, who presented a nice viewpoint of his vision of computational storage and its underlying benefits that make the overall infrastructure more rich and efficient, and how to bring compute to the drives.  For a summary, watch Dave Eggleston of In-Cog Computing who led Tuesday and Wednesday panels with the mainstage speakers that provided a wide ranging discussion on the Summit’s key topics. SOS: What do you see as the top takeaways from the Summit presenters? DM: I see three:

1. Infrastructure, applications, and use cases were paramount themes across a number of presentations
2. Tighter coupling of technologies.  Cheolmin Park of Samsung, in his CXL and UCIe presentation, discussed how we already have point technologies that now need to interact together.  There is also the Persistent Memory/SSD/DRAM combination – a tiered memory configuration talked about for years.  We are seeing deployment use cases where the glue is interfacing the I/O technology with CXL and UCIe.
3. Another takeaway strongly related to the above is heterogeneous operations and compute.  Compute can’t reside in one central location for efficiency.  Rather, it must be distributed – addressing real-time analytics and decision making to support applications.

SOS: What upcoming activities should Summit viewers plan to attend and why? DM: Put Flash Memory Summit, August 1-4, 2022 on your calendars.  Here SNIA will go deeper into areas we explored at the Summit. First, join SNIA Compute, Memory, and Storage Initiative (CMSI), underwriter of the PM+CS Summit, as we meet in person for the first time in a long time at the SNIA Reception on Monday evening August 1 at the Santa Clara Convention Center from 5:30 pm – 7:00 pm. Along with our SNIA teammates from the SNIA Storage Management Initiative, network with colleagues and share an appetizer or two as we gear up for three full days of activities. At the Summit, the SNIA-sponsored System Architecture Track will feature a day on persistent memory, a day on CXL, and a day on computational storage.  SNIA will also lead sessions on form factors, ethernet SSDs, sustainability, and DNA data storage.  I am Track Manager of the Artificial Intelligence Applications Track, where we will see how technologies like computational storage and AI work hand-in-hand. SNIA will have a Demonstration Pavilion at booth 725 in the FMS Exhibit Hall with live demonstrations of computational storage applications, persistent memory implementations, and scalable storage management with SNIA Alliance Partners; hands-on form factor displays; a Persistent Memory Programming Workshop and Hackathon; and theater presentations on standards. Full details are at www.flashmemorysummit.com In September, CMSI will be at the SNIA Storage Developer Conference where we will celebrate SNIA’s 25th anniversary and gather in person for sessions, demonstrations, and those ever popular Birds-of-a-Feather sessions.  Find the latest details at www.storagedeveloper.org. SOS: Any final thoughts? DM: On behalf of SNIA CMSI and the PM+CS Summit Planning Team, I’d like to thank all those who planned and attended our great event.  We are progressing in the right direction, beginning to talk the same language that application developers and solution providers understand.  We’ll keep building our strategic collaboration across different worlds at FMS and SDC.  I appreciate the challenges and working together. The post Summit Success – and A Preview of What’s To Come first appeared on SNIA Compute, Memory and Storage Blog.

As covered in our first xPU webcast “SmartNICs and xPUs: Why is the Use of Accelerators Accelerating,” we discussed the trend to deploy dedicated accelerator chips to assist or offload the main CPU. These new accelerators (xPUs) have multiple names such as SmartNIC, DPU, IPU, APU, NAPU. If you missed the presentation, I encourage you to check it out in the SNIA Educational Library where you can watch it on-demand and access the presentation slides. This second webcast in this SNIA Networking Storage Forum xPU webcast series is “xPU Accelerator Offload Functions” where our SNIA experts will take a deeper dive into the accelerator offload functions of the xPU. We’ll discuss what problems the xPUs are coming to solve, where in the system they live, and the functions they implement, focusing on:

• Network Offloads
  • Virtual switching and NPU
  • P4 pipelines
  • QoS and policy enforcement
  • NIC functions
  • Gateway functions (tunnel termination, load balancing, etc)
• Security Offloads
  • Encryption
  • Policy enforcement
  • Key management and crypto
  • Regular expression matching
  • Firewall
  • Deep Packet Inspection (DPI)
• Compute Offloads
  • AI calculations, model resolution
  • General purpose processing (via local cores)
  • Emerging use of P4 for general purpose
• Storage Offloads
  • Compression and data at rest encryption
  • NVMe-oF offload
  • Regular expression matching
  • Storage stack offloads

This webcast will be live on June 29, 2022 at 11:00 am PT/2:00 pm ET. I encourage you to register today and bring your questions for our experts. We look forward to seeing you.

The complex and changeable structure of edge computing, together with its network connections, massive real-time data, challenging operating environment, distributed edge cloud collaboration, and other characteristics, create a multitude of security challenges. It was the topic of our SNIA Networking Storage Forum (NSF) live webcast “Storage Life on the Edge: Security Challenges” where SNIA security experts Thomas Rivera, CISSP, CIPP/US, CDPSE and Eric Hibbard, CISSP-ISSAP, ISSMP, ISSEP, CIPP/US, CIPT, CISA, CDPSE, CCSK debated as to whether existing security practices and standards are adequate for this emerging area of computing. If you missed the presentation, you can view it on-demand here.

It was a fascinating discussion and as promised, Eric and Thomas have answered the questions from our live audience.

Q. What complexities are introduced from a security standpoint for edge use cases?

A. The sheer number of edge nodes, the heterogeneity of the nodes, distributed ownership and control, increased number of interfaces, fit-for-use versus designed solution, etc. complicate the security aspects of these ecosystems. Performing risk assessments and/or vulnerability assessments across the full ecosystem can be extremely difficult; remediation activities can be even harder.

Q. How is data privacy impacted and managed across cloud to edge applications?

A. Movement of data from the edge to core systems could easily cross multiple jurisdictions that have different data protection/privacy requirements. For example, personal information harvested in the EU might find its way into core systems in the US; in such a situation, the US entity would need to deal with GDPR requirements or face significant penalties. The twist is that the operator of the core systems might not know anything about the source of the data.

Q. What are the priority actions that customers can undertake to protect their data?

A. Avoid giving personal information. If you do, understand your rights (if any) as well as how it will be used, protected, and ultimately eliminated.

This session is part of our “Storage Life on the Edge” webcast series. Our next session will be “Storage Life on the Edge: Accelerated Performance Strategies” where we will dive into the need for faster computing, access to storage, and movement of data at the edge as well as between the edge and the data center. Register here to join us on July 12, 2022. You can also access the other presentations we’ve done in this series at the SNIA Educational Library.

The complex and changeable structure of edge computing, together with its network connections, massive real-time data, challenging operating environment, distributed edge cloud collaboration, and other characteristics, create a multitude of security challenges. It was the topic of our SNIA Networking Storage Forum (NSF) live webcast “Storage Life on the Edge: Security Challenges” where SNIA security experts Thomas Rivera, CISSP, CIPP/US, CDPSE and Eric Hibbard, CISSP-ISSAP, ISSMP, ISSEP, CIPP/US, CIPT, CISA, CDPSE, CCSK debated as to whether existing security practices and standards are adequate for this emerging area of computing. If you missed the presentation, you can view it on-demand here. It was a fascinating discussion and as promised, Eric and Thomas have answered the questions from our live audience. Q. What complexities are introduced from a security standpoint for edge use cases? A. The sheer number of edge nodes, the heterogeneity of the nodes, distributed ownership and control, increased number of interfaces, fit-for-use versus designed solution, etc. complicate the security aspects of these ecosystems. Performing risk assessments and/or vulnerability assessments across the full ecosystem can be extremely difficult; remediation activities can be even harder. Q. How is data privacy impacted and managed across cloud to edge applications? A. Movement of data from the edge to core systems could easily cross multiple jurisdictions that have different data protection/privacy requirements. For example, personal information harvested in the EU might find its way into core systems in the US; in such a situation, the US entity would need to deal with GDPR requirements or face significant penalties. The twist is that the operator of the core systems might not know anything about the source of the data. Q. What are the priority actions that customers can undertake to protect their data? A. Avoid giving personal information. If you do, understand your rights (if any) as well as how it will be used, protected, and ultimately eliminated. This session is part of our “Storage Life on the Edge” webcast series. Our next session will be “Storage Life on the Edge: Accelerated Performance Strategies” where we will dive into the need for faster computing, access to storage, and movement of data at the edge as well as between the edge and the data center. Register here to join us on July 12, 2022. You can also access the other presentations we’ve done in this series at the SNIA Educational Library.

In our SNIA Networking Storage Forum webcast series, “Storage Life on the Edge” we’ve been examining the many ways the edge is impacting how data is processed, analyzed and stored. I encourage you to check out the sessions we’ve done to date:

• Managing Data from the Edge to the Cloud and Back
• Edge Storage Use Cases
• Edge Security Challenges

On July 12, 2022, we continue the series with “Storage Life on the Edge: Accelerated Performance Strategies” where our SNIA experts will discuss the need for faster computing, access to storage, and movement of data at the edge as well as between the edge and the data center, covering:

• The rise of intelligent edge locations
• Different solutions that provide faster processing or data movement at the edge
• How computational storage can speed up data processing and transmission at the edge
• Security considerations for edge processing

We look forward to having you join us to cover all this and more. We promise to keep you on the edge of your virtual seat! Register today.

In our SNIA Networking Storage Forum webcast series, “Storage Life on the Edge” we’ve been examining the many ways the edge is impacting how data is processed, analyzed and stored. I encourage you to check out the sessions we’ve done to date:

• Managing Data from the Edge to the Cloud and Back
• Edge Storage Use Cases
• Edge Security Challenges

On June 15, 2022, we continue the series with “Storage Life on the Edge: Accelerated Performance Strategies” where our SNIA experts will discuss the need for faster computing, access to storage, and movement of data at the edge as well as between the edge and the data center, covering:

• The rise of intelligent edge locations
• Different solutions that provide faster processing or data movement at the edge
• How computational storage can speed up data processing and transmission at the edge
• Security considerations for edge processing

We look forward to having you join us to cover all this and more. We promise to keep you on the edge of your virtual seat! Register today.

Our 10^th annual Persistent Memory + Computational Storage Summit is right around the corner on May 24 and 25, 2022.  We remain virtual this year, and hope this will offer you more flexibility to watch our live-streamed mainstage sessions, chat online, and catch our always popular Computational Storage birds-of-a-feather session on Tuesday afternoon without needing a plane or hotel reservation!

As David McIntyre of Samsung, the 2022 PM+CS Summit chair, says in his 2022 Summit Preview Video, “You won’t want to miss this event!”   

This year, the Summit agenda expands knowledge on computational storage and persistent memory, and also features new sessions on computational memory, Compute Express Link ^TM (CXL)^TM, NVM Express, SNIA Smart Data Accelerator Interface (SDXI), and Universal Chiplet Interconnect Express (UCIe).

We thank our many dynamic speakers who are presenting an exciting lineup of talks over the two days, including:

• Yang Seok Ki of Samsung on Innovation with SmartSSD for Green Computing
• Charles Fan of MemVerge on Persistent Memory Breaks Through the Clouds
• Gary Grider of Los Alamos National Labs on HPC for Science Based Motivations for Computation Near Storage
• Alan Benjamin of the CXL Consortium on Compute Express Link (CXL): Advancing the Next Generation of Data Centers
• Cheolmin Park of Samsung on CXL and The Universal Chiplet Interconnect Express (UCIe)
• Stephen Bates and Kim Malone of NVM Express on NVMe Computational Storage - An Update on the Standard
• Andy Walls of IBM on Computational Storage for Storage Applications

Our full agenda is at www.snia.org/pm-summit.

We’ll have great networking opportunities, a virtual reception, and the ability to connect with leading companies including Samsung, MemVerge, and SMART Modular who are sponsoring the Summit. 

Complimentary registration is now available at https://www.snia.org/events/persistent-memory-summit/pm-cs-summit-2022-registration.  We will see you there!