Richelle Ahlvers runs Technology Initiatives and Ecosystem Enabling for the Datacenter and AI business for Intel, promoting and driving enablement of new technologies and standards strategies. Richelle has spent over 30 years in Enterprise R&D teams in a variety of technical roles, spanning architecture, design and development of software, firmware, and hardware, for everything from enterprise storage solutions to CPUs. Richelle has been engaged with industry standards initiatives for many years and is actively engaged with many groups including SNIA, DMTF, NVMe, OFA and UCIe. She is Vice-Chair of the SNIA Board of Directors, Chair of the Storage Management Initiative, leads the SSM Technical Work Group developing the Swordfish Scalable Storage Management API, and is a former SNIA Technical Council Chair. She serves on the DMTF Board of Directors as the VP of Alliances.

Mike Allison is a Sr. Director in the Samsung Semiconductor Product Planning and Business Enablement team focusing on standards for existing and future NAND products. He is a participating member of SNIA, NVM Express, DMTF, PCI-SIG, and OCP. He is a member of the NVMe Board of Directors, chair of the NVMe Errata Task Group, and represents the OCP Storage Project on the OCP Steering Committee. Over a 41-year career, Mike has been an embedded firmware engineer and architect on products for laser beam recorders, fighter aircraft, graphics cards, high end servers, and is now focusing on Solid State Drives. He holds 38 patents and earned a BSEE/CS at University of Colorado, Boulder.

Curtis Ballard is a Distinguished Technologist with Hewlett Packard Enterprise in the HPE Storage organization where he works on storage architecture, intellectual property, and storage technology strategy with a focus on enabling new storage technologies. Curtis has 30 years of experience in storage and storage interfaces technologies where he has worked in product design teams for storage arrays, storage enclosures, tape drives, tape libraries, and magneto optical drives. He has developed hardware designs for storage interfaces and storage controllers as well as firmware for motion control, storage interfaces, user interface, and embedded operating systems. In addition to Storage Platform development for HPE, Curtis also represents HPE in several industry organizations. Curtis is a treasurer for the NVM Express Board of Directors, is a member of the SNIA Technical Council, and is the vice-chair of the INCITS/SCSI (T10) Storage Interfaces Technical Committee where he has been the editor for several SCSI standards. He is an inventor on over 40 US patents in the storage industry across electrical, software, and mechanical disciplines.

Ralph Böhme is a member of the international Samba Team and leads the Samba team at SerNet.

Swati Chawdhary is a Senior Manager at Samsung. She has diverse experience in Storage domain. Her recent work focuses on the test and development of NVMe-oF/NVMe controllers and All Flash Array reference designs. Before joining Samsung, she worked at Chelsio Communications, where she contributed to the development of their Unified Wire Adapters. She has participated in conferences like IEEE Wintechcon, FMS, SDC US/India and NVMe developer Days. She earned a Bachelor's degree in Computer Science from Pune University.

Christofferson brings more than 25 years of content creation, content management and storage expertise focused on the methods and technologies needed to use and manage massive volumes of data. Most recently, he was CEO of StrongBox Data Solutions, an autonomous data management and data archiving provider. Previously, Christofferson served as CMO at Arcitecta IP Pty Ltd, a comprehensive data management platform company, and as Director, Storage Product Marketing at SGI for its InfiniteStorage products.

Anthony Constantine is a Distinguished Member of Technical Staff responsible for Storage Standards at Micron. He is very active in SNIA as co-chair of the SFF TWG, an author for several EDSFF specifications, and author or contributor to several other SFF TWG specifications. He is also a past member of the SNIA Technical Council. In addition, Anthony contributes to PCI-SIG, JEDEC, NVMe, and Open Compute Platform (OCP). Anthony has over 25 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Clarete Crasta is a Principal Engineer in Hewlett Packard Enterprise, currently working in the HPC and AI Advance Development group. She is a well-recognized technical architect and has built a solid reputation over 20 years with deep system software expertise in High Performance Computing, memory and storage technologies, operating systems kernel, platform & IO, and virtualization. Her ability to drive and lead teams, focus on customers, willingness to take up any complex work in newer areas, effective communication skills, and active collaboration has gained her acceptance across the community. Clarete has experience leading and collaborating across teams, business units, customers and partners. She is a co-inventor on 13 US filed patents and has co-authored 7 publications. She has presented at various conferences such as SNIA CMS, SNIA SDC, CUG, GHCI on Fabric Attached Memory and related topics. She has worked as a member of the technical committee and review board for GHCI, IEEE and is serving as Industry Track Chair for IC2E. She holds a master’s degree in software engineering and bachelor’s in electrical engineering.

Josh Freilich is a Principal Engineer at Everpure, where he designs data storage systems operating at extreme scale. Over the past decade, he has led the development of innovative solutions in host-based NAND management, I/O scheduling, storage virtualization, and virtual memory management. He holds dozens of issued patents in these domains. Josh earned his Bachelor of Science in Computer Science and Applied Mathematics from Brown University, with a focus on systems architecture and probability theory.

Mr. Gervasi has nearly 5 decades of experience in high speed memory subsystem definition, design, and product development. He piloted the definition of Double Data Rate SDRAM since its earliest inception, authoring the first standard specification, and created the Automotive SSD standard. With MPS, Bill is driving some of the memory and storage system management mechanisms for a post-quantum world. He received the JEDEC Technical Excellence award, their highest honor, in 2020.

Jason is a Distinguished Engineer at Dell Technologies, working in the Storage Chief Technology Office. His role involves leading the development of next-generation storage and network protocols for both Public and Private Clouds. Jason also serves as Chair of the SNIA Accelerated Object I/O Technical Working Group. Throughout his career, Jason has focused on enterprise storage and meeting the needs of customers who want to expand beyond the traditional on-premises data center. He enjoys collaborating with customers and partners to understand their requirements when transforming their business. In his personal life, Jason is passionate about running marathons and baking artisan bread. He lives in Newton, Massachusetts, with his wife and their three children.

Alessandro Goncalves is a Storage Solutions Architect specializing in high-performance storage systems, AI/ML infrastructure, and workload-aware performance engineering. Currently at Solidigm, he focuses on architecting and benchmarking SSD-based solutions for emerging AI and inference workloads, collaborating with organizations such as MLCommons to evaluate next-generation storage behavior for data-intensive AI pipelines. His background includes persistent memory architecture and performance engineering work at Intel, where he contributed to solutions involving Optane and large-scale storage performance analysis across enterprise and hyperscale environments. His recent work centers on AI-oriented storage observability, workload fingerprinting, vector database benchmarking, KV-cache infrastructure, and cross-layer latency attribution for modern storage systems.

Adam Gray is Principal Software Engineer at IBM Cloud Object Storage and has nearly 15 years of experience in object storage. Adam primarily works in distributed systems, hyperscale computing, and mentoring students and new hires. Adam has 40+ patents issued by the USPTO and is an IBM Master Inventor. He earned his B.S. in Computer Science from Indiana University and lives and works from Chicago, Illinois.

Technical Director, Micron Technology; Co-Chair, CXL Consortium Software and Systems Working Group John Groves has been a kernel and system software developer for decades, working on memory management, file systems and data storage in several Unix variants prior to Linux. John serves the CXL Consortium as co-chair of the Software and Systems Working Group (SSWG), and is a contributor to the CXL specification - particularly in the areas of fabric management, shared memory and dynamic capacity devices (DCDs). John is also the creator and primary author of famfs – the Fabric-Attached Memory File System – which is working its way toward inclusion the Linux Kernel. John has spoken on famfs at the last two Linux Plumbers conferences (2023 and 2024) as well as the Linux Storage, Filesystem and Memory Management (LSFMM) summits in 2024 and 2025 and Usenix FAST in 2025. John is an expert in system software development, cache coherency, memory models and CXL.

Chandra Guda is a Senior Member of Technical Staff (SMTS) System Architect based in San Jose, California, where he focuses on storage next architectures for GPU‑accelerated and high‑performance computing workloads. His current work spans NVMe, AI workloads and studying heterogeneous CPU–GPU data paths, with an emphasis on scalable, low‑latency, and secure storage systems. He previously held roles in firmware architecture and staging technologies at WDC and developed firmware for SSDs, HDDs. He holds a Masters Engineering degree and brings over two decades of experience in system architecture and storage technologies and hold 30+ Patents in Storage architecture technology.

Jonmichael Hands is CEO of FarmGPU and AI Technologist at Solidigm, where he focuses on the intersection of storage, AI infrastructure, and emerging workloads. He brings over a decade of experience from Intel’s Non-Volatile Memory Solutions Group, where he led product line management, strategic planning, and technical marketing for data center SSDs. Jonmichael has held key industry leadership roles, including Chair of NVMe Marketing and Co-Chair of the SNIA SSD Special Interest Group, and has contributed to storage and sustainability initiatives within the Open Compute Project. He previously served as VP of Storage at Chia Network and remains an advisor. Jonmichael is Chairman of the Board of the Circular Drive Initiative (CDI), a 501(c)(6) organization advancing secure drive reuse and circular business models across the storage industry. He began his career at Sun Microsystems designing storage arrays (JBODs) and holds a degree in Electrical Engineering from the Colorado School of Mines.

Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became highly respected as an analyst for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com. His reports can be purchased at www.Objective-Analysis.com

Erich Haratsch is Senior Distinguished Engineer at Marvell, where he leads architecture definition for SSD and storage controllers. 

Before Marvell, he worked at Seagate and LSI on SSD and HDD controllers across multiple product generations, and earlier at Agere Systems on HDD controller development. 

He began his career at AT&T and Lucent Bell Labs, contributing to Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. 

Erich is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. 

He is a Senior Member of IEEE and holds MS and PhD degrees from the Technical University of Munich, Germany.

Steffen has more than 25 years of industry experience in product, technology, business & corporate development as well as strategy roles. He served as Senior Vice President, Business Development, Data Storage at Twist Bioscience and held executive management positions at various semiconductor companies including Western Digital, Everspin, SandForce, and Seagate Technology. At Everspin, Steffen was part of the Marketing team that drove the introduction of the world’s first commercial Spin-Torque MRAM product offering. He has been deeply engaged in various industry trade associations and standards organizations including cofounding the DNA Data Storage Alliance in 2020 as well as the USB Flash Drive Alliance, serving as their president from 2003 to 2007. He holds an Economic Electrical Engineering degree (EEE) from the Technical University of Darmstadt, Germany.

Michael serves as Chair for the SNIA Cloud Storage Technologies (CST) group, where he leads community building and promotion of the SNIA Cloud Object Storage (COS) Plugfest and SNIA COS Test Tools technical work group. With over thirty years' experience in the storage industry, Michael energetically builds trust, consensus and productivity among collaborative teams, having served in a variety of roles including Intel Xeon Data Storage Strategist, Seagate Outbound HPC Storage Marketing, IBM Enterprise & Midrange Disk Product Management, IBM eServer Storage Architect, and Chairman of the Board for the Fibre Channel Industry Association (FCIA).

Chih-Tsung Huang is the Senior Director of Hardware Engineering in the Common Hardware Group. Chih-Tsung is responsible for delivering Sustainable AI infrastructure solutions for silicon, hardware systems and optics in Cisco’s switching, routing, optical, access and IoT portfolios. Chih-Tsung has over 100 US and Global patents covering a breadth of topics including but not limited to sustainability, silicon, FPGA, networking, compute, security and storage.

Howard is the chair of the INCITS/Fibre Channel techncial committee and remains actively involved in the development of Fibre Channel standards. As Broadcom's technical liaison to many Fibre Channel industry partners, Howard joined the forces of the Fibre Channel ecosystem vendors to deliver products based on the Fabric Notifications standards and architecture for the Fibre Channel industry. These efforts developed solutions that leveraged Fabric Notifications in the formation of autonomous SAN technology. Howard began his career in 1984 developing configuration applications for 3270 Cluster Controllers for McDATA Corporation in Boulder, Colorado. In 1993, in partnership with IBM, Howard was part of the team that created the ESCON Director Models 3/4/5 as well as the FICON to ESCON Bridge. As technical leader, he directed the efforts of the technical teams that expanded IBM’s original storage-area networks (SAN) from ESCON to FICON. In 2007, Howard joined Brocade, a Broadcom company, as a member of the Fabric Operating Systems Architecture group and is responsible for the technical strategy relating to Brocade’s mainframe infrastructure offerings. His industry experience lead to a featured interview in Enterprise Executive (2019, issue 6), where he discussed the future of the mainframe, FICON, and Fibre Channel. Today, Howard is an active member of the Brocade SAN Networking (BSN) division of Broadcom Limited and continues his technical leadership in enterprise networking solutions. With more than 40-years of professional experience in high-end processing environments, Howard remains an active advocate of Fibre Channel.

John Mazzie is a Member of Technical Staff (MTS) Systems Performance Engineer based in Austin, TX, where he is focused on application performance analysis and tracing for AI workloads, as well as automation and tool development. John is also a current member representing Micron on the SNIA Technical Council. He previously held roles as a Senior Storage Engineer at Dell, Inc. John holds an M.S. in electrical engineering from West Virginia University.

Stefan Metzmacher is working for SerNet and is a member of the international Samba Team. His focus is spread into all areas of Samba including WINS-Replication, DRS-Replication, Authentication, SMB*, DCERPC and a lot of architectural [re-]designs of common code.

Chris J. Newburn, who goes by CJ, is a Distinguished Engineer who drives HPC strategy and the technical IO roadmap in NVIDIA GPU Cloud, focused on pushing the envelope for storage and networking programming models at scale, data center architecture and security, and scaled systems. 

He is a community builder with a passion for building an ecosystem that extends the core capabilities of hardware and software platforms from HPC into AI, data science, and visualization. 

He co-leads the Storage-Next effort to optimize products for IOPs/TCO. He tinkers with and leverages NVIDIA and vendor products in a lab packed with scaled compute, storage and networking gear to apply and extend new tech. He's delighted to have worked on volume products that his Mom used and that help researchers do their life's work in science that previously wasn't possible.

Sergei Platonov is the Vice President of Strategy at Xinnor, a technology company specializing in storage solutions. Sergei's journey in the tech industry began in 2010 when he graduated from the university, earning a degree in Computer Science. With a strong passion for storage technologies, he joined SDS start-up in 2009. Throughout his career, Sergei has been instrumental in the development of Storage Area Networks (SAN) and has focused on the research and implementation of cutting-edge technologies such as Flash, NVMe (Non-Volatile Memory Express), CXL (Compute Express Link), and storage performance improvement techniques. His expertise in these areas has enabled Xinnor to create highly efficient and reliable storage solutions that cater to the evolving needs of businesses. Sergei's contributions to the industry go beyond development work. He is a recognized thought leader and has delivered more than 30 presentations at conferences, sharing his insights and knowledge on storage technologies. Additionally, he has authored numerous articles, shedding light on the advancements in Storage Class Memory and its impact on storage performance.

Mahinder Saluja, Director of SSD Technology and Pathfinding at KIOXIA America, Inc., has 20+ years of engineering leadership in innovative storage technologies development, building teams and product delivery. He has several pending storage related patents.

David Slik is a scientist and data storage researcher at the Huawei Canadian Research Institute. Before working at Huawei, he was a Technical Director at NetApp and a co-founder of Bycast, where he led the development of StorageGRID. He has 25+ years of experience in the design, development and productization of high-performance distributed storage systems, resulting in over 90 granted patents. David is an author of two ISO/IEC standards, a contributor to five other storage industry standards organizations, and a chair of the Cloud Storage Technical Work Group at SNIA and the Power Work Group at MLCommons.

Gary Smerdon is the CEO and founder of MEXT. Before MEXT, Gary served as CEO at TidalScale and held numerous leadership positions including at Fusion-io, LSI, and AMD. He is a recognized innovator having led key efforts around industry transitions in networking, storage, and computing.

Ross Stenfort is a Distinguished Engineer at SanDisk, driving storage innovation and industry collaboration. He is an active collaborator with industry organizations including OCP, SNIA/SFF, and NVM Express. Over his career, he has developed Storage Systems, SSDs, ROCs and HBAs and achieving 40+ patents. With 30+ years of experience across Meta, CNEX, Seagate, LSI, SandForce, SiliconStor, and Adaptec, Ross brings a broad and deep perspective on the storage ecosystem. He holds a B.S. in Electronic Engineering from Cal Poly, San Luis Obispo.

Curtis Stevens (Strategist, Seagate Technology) has been working in the storage industry for over 35 years with experience in host side drivers, HBA design, Hard disk drives, SSD’s, SAS/SATA/USB/1394/etc. Curtis is the technical editor for standards and specifications in INCITS T10, INCITS T13, SATA-IO, USB-IF, NVMe, and others. Curtis has helped invent and standardize technologies in the areas of Bootable CD-ROM, PATA-SATA bridges, USB Printers, USB Mass Storage, translating SAS to SATA, 4K/512e sector sizes, NVMe Zoned Name Spaces, and most recently, Drive Regeneration/depopulation & Translating SAS to NVMe.

Himabindu Tummala is a Distinguished Engineer based in Hopkinton, Massachusetts, with deep expertise in large‑scale storage systems and distributed data architectures. Her work focuses on building AI‑ready data platforms, spanning data preparation and object‑based infrastructures that support modern analytics and AI workloads.

Wes Vaske is a Senior Member of Technical Staff at Micron Technology. As a Storage Solutions Architect with over 15 years of experience in data center storage systems, he is currently focused on developing high-performance NVMe solutions for AI workloads. 

He has been a lead contributor to the MLPerf Storage Working Group helping to define industry benchmarks for AI storage performance. 

Wes is a frequent presenter at Future of Memory and Storage (FMS) and SNIA Developer Conference (SDC) and Chairs the SNIA AI Data Workloads Technical Working Group (TWG) Prior to his current role, Wes was a Systems Performance Engineer with the Data Center Workloads Engineering team for more than a decade, where he pioneered system observation, tracing, and analysis tools as well as developing automation frameworks enabling reproducible and insightful performance analysis across diverse environments that have become foundational to Micron’s workload-first product development strategy. 

His earlier career includes performance engineering for Oracle RAC database systems at Dell Technologies. Wes holds a B.S. in Physics from Iowa State University and continues to drive innovation at the intersection of storage, AI, and systems performance.

Diman Zad Tootaghaj is a Senior Researcher at Hewlett Packard Labs in California. She earned her Ph.D. in Computer Science and Engineering from The Pennsylvania State University, and her B.S. and M.S. degrees in Electrical Engineering from Sharif University of Technology. Her research focuses on advancing computer networks and distributed systems, with interests spanning serverless computing, sustainability in computing, network programmability, SmartNICs, SD-WAN, edge-as-a-service platforms, serverless orchestration and auto-scaling, CXL, optimization algorithms, and consensus protocols.